forked from M-Labs/artiq
coreanalyzer: add WB stb signal
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parent
039ced6637
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1573ff5fc1
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@ -240,12 +240,15 @@ class DDSHandler:
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self._decode_ad9914_write(message)
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class WishboneHandlerMixin:
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def __init__(self, read_bit):
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class WishboneHandler:
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def __init__(self, vcd_manager, name, read_bit):
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self._reads = []
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self._read_bit = read_bit
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self.stb = vcd_manager.get_channel("{}/{}".format(name, "stb"), 1)
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def process_message(self, message):
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self.stb.set_value("1")
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self.stb.set_value("0")
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if isinstance(message, OutputMessage):
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logger.debug("Wishbone out @%d adr=0x%02x data=0x%08x",
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message.timestamp, message.address, message.data)
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@ -270,11 +273,11 @@ class WishboneHandlerMixin:
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raise NotImplementedError
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class SPIMasterHandler(WishboneHandlerMixin):
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class SPIMasterHandler(WishboneHandler):
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def __init__(self, vcd_manager, name):
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super().__init__(read_bit=0b100)
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self.channels = {}
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with vcd_manager.scope("spi/{}".format(name)):
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super().__init__(vcd_manager, name, read_bit=0b100)
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for reg_name, reg_width in [
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("config", 32), ("chip_select", 16),
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("write_length", 8), ("read_length", 8),
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