forked from M-Labs/artiq
coreanalyzer: add SPIMaster support
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41e8acf3ad
commit
7519408857
@ -232,6 +232,69 @@ class DDSHandler:
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self._decode_ad9914_write(message)
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class WishboneHandlerMixin:
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def __init__(self, read_bit):
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self._reads = []
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self._read_bit = read_bit
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def process_message(self, message):
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if isinstance(message, OutputMessage):
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logger.debug("Wishbone out @%d adr=0x%02x data=0x%08x",
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message.timestamp, message.address, message.data)
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if message.address & self._read_bit:
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read = self._reads.pop(0)
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self.process_read(
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message.address & ~self._read_bit,
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read.data,
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read.rtio_counter - message.timestamp)
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else:
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self.process_write(message.address,
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message.data)
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if isinstance(message, InputMessage):
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logger.debug("Wishbone in @%d data=0x%08x",
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message.rtio_counter, message.data)
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self._reads.append(message)
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def process_write(self, address, data):
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raise NotImplementedError
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def process_read(self, address, data, read_slack):
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raise NotImplementedError
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class SPIMasterHandler(WishboneHandlerMixin):
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def __init__(self, vcd_manager, name):
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super().__init__(read_bit=0b100)
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self.channels = {}
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for reg_name, reg_width in [
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("config", 32),
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("chip_select", 16), ("write_length", 8), ("read_length", 8),
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("write", 32), ("read", 32)]:
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self.channels[reg_name] = vcd_manager.get_channel(
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"/".join((name, reg_name)), reg_width)
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def process_write(self, address, data):
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if address == 0:
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self.channels["write"].set_value("{:032b}".format(data))
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elif address == 1:
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self.channels["chip_select"].set_value(
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"{:08b}".format(data & 0xffff))
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self.channels["write_length"].set_value(
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"{:08b}".format(data >> 16 & 0xff))
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self.channels["read_length"].set_value(
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"{:08b}".format(data >> 24 & 0xff))
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elif address == 2:
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self.channels["config"].set_value("{:032b}".format(data))
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else:
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raise ValueError("bad address %d", address)
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def process_read(self, address, data, read_slack):
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if address == 0:
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self.channels["read"].set_value("{:032b}".format(data))
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else:
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raise ValueError("bad address %d", address)
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def _extract_log_chars(data):
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r = ""
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for i in range(4):
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@ -331,6 +394,11 @@ def create_channel_handlers(vcd_manager, devices, ref_period,
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dds_onehot_sel, dds_sysclk)
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channel_handlers[dds_bus_channel] = dds_handler
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dds_handler.add_dds_channel(name, dds_channel)
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if (desc["module"] == "artiq.coredevice.spi" and
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desc["class"] == "SPIMaster"):
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channel = desc["arguments"]["channel"]
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channel_handlers[channel] = SPIMasterHandler(
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vcd_manager, name)
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return channel_handlers
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