David Nadlinger
720838a23e
gateware/suservo: Avoid magic number for activation delay width
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Mostly for documentation purposes; 8 bits ought to be enough for
everyone.
2019-06-14 23:45:40 +01:00
David Nadlinger
a565f77538
Add gateware input event counter
2019-01-15 10:55:07 +00:00
6df4ae934f
eem: name the servo submodule
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This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos
close #1201
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:40 +01:00
2af6edb8f5
eem: fix reset/sync in suservo
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-13 13:00:54 +00:00
3538444876
urukul: add sync_in to eem0-7 name
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:32 +01:00
0433e8f4fe
urukul: add sync_in generator
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:30 +01:00
9b016dcd6d
eem: support specifying I/O standard
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Xilinx FPGAs require different LVDS I/O standard names depending on I/O bank voltage.
2018-07-17 18:55:17 +08:00
b6c70b3cb0
eem: add Zotino monitoring. Closes #1095
2018-07-15 15:35:04 +08:00
701c93d46c
grabber: add false path constraints
2018-07-10 14:28:23 +08:00
c4e3c66265
grabber: add clock constraint
2018-07-10 12:37:32 +08:00
540bdae99c
grabber: enable DIFF_TERM on inputs
2018-07-01 09:28:51 +08:00
bb87976d4f
suservo: docstring fixes, revert parametrization of r_rtt
2018-06-04 07:27:17 +00:00
07a1425e51
SUservo EEM docs
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add documentation to eem.SUServo. Change parameterization of t_rtt to include delays on Sampler, as this seems simpler and more robust to changing RTIO frequencies in the future.
c.f. #1046
2018-06-04 08:51:28 +02:00
f50aef1a22
suservo: extract boilerplate
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closes #1041
2018-06-01 15:37:07 +00:00
563e434e15
eem: finalize grabber support
2018-05-28 22:43:06 +08:00
80c69da17e
eem: add Grabber IOs and CC
2018-05-28 11:16:23 +08:00
bb248970df
style
2018-05-28 10:40:05 +08:00
19efd8b13e
kasli: refactor EEM code
2018-05-24 18:41:54 +08:00
