2014-07-11 00:13:37 +08:00
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from artiq.language.core import *
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2015-09-30 23:41:14 +08:00
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from artiq.language.types import *
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2014-05-31 00:20:13 +08:00
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from artiq.language.units import *
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2014-09-05 12:03:22 +08:00
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2015-06-26 18:05:11 +08:00
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_PHASE_MODE_DEFAULT = -1
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2015-05-08 14:44:39 +08:00
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# keep in sync with dds.h
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2014-11-21 04:32:56 +08:00
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PHASE_MODE_CONTINUOUS = 0
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PHASE_MODE_ABSOLUTE = 1
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PHASE_MODE_TRACKING = 2
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2016-03-29 05:25:40 +08:00
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@syscall(flags={"nowrite"})
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2016-03-09 17:12:50 +08:00
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def dds_init(time_mu: TInt64, bus_channel: TInt32, channel: TInt32) -> TNone:
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2015-08-11 00:25:48 +08:00
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raise NotImplementedError("syscall not simulated")
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2016-08-11 08:31:17 +08:00
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@syscall(flags={"nowrite"})
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def dds_init_sync(time_mu: TInt64, bus_channel: TInt32,
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channel: TInt32, sync_delay: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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2016-03-29 05:25:40 +08:00
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@syscall(flags={"nowrite"})
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2016-03-09 17:12:50 +08:00
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def dds_set(time_mu: TInt64, bus_channel: TInt32, channel: TInt32, ftw: TInt32,
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pow: TInt32, phase_mode: TInt32, amplitude: TInt32) -> TNone:
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2015-08-11 00:25:48 +08:00
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raise NotImplementedError("syscall not simulated")
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2016-03-29 05:25:40 +08:00
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@syscall(flags={"nowrite"})
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2016-03-09 17:12:50 +08:00
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def dds_batch_enter(time_mu: TInt64) -> TNone:
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2015-08-11 00:25:48 +08:00
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raise NotImplementedError("syscall not simulated")
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2016-03-29 05:25:40 +08:00
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@syscall(flags={"nowrite"})
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2016-03-09 17:12:50 +08:00
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def dds_batch_exit() -> TNone:
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2015-08-11 00:25:48 +08:00
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raise NotImplementedError("syscall not simulated")
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2015-05-09 14:47:40 +08:00
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class _BatchContextManager:
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2016-04-07 06:38:31 +08:00
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kernel_invariants = {"core", "core_dds"}
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2016-03-28 08:05:29 +08:00
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2016-03-09 17:12:50 +08:00
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def __init__(self, core_dds):
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self.core_dds = core_dds
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self.core = self.core_dds.core
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2015-05-09 14:47:40 +08:00
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@kernel
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def __enter__(self):
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2016-03-09 17:12:50 +08:00
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self.core_dds.dds_batch_enter()
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2015-05-09 14:47:40 +08:00
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@kernel
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def __exit__(self, type, value, traceback):
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2016-03-09 17:12:50 +08:00
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self.core_dds.dds_batch_exit()
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2015-05-09 14:47:40 +08:00
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2016-03-09 17:12:50 +08:00
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class CoreDDS:
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"""Core device Direct Digital Synthesis (DDS) driver.
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Gives access to the DDS functionality of the core device.
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2015-05-08 22:17:06 +08:00
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2016-03-09 17:12:50 +08:00
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:param sysclk: DDS system frequency. The DDS system clock must be a
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phase-locked multiple of the RTIO clock.
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"""
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2016-03-28 08:05:29 +08:00
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2016-04-07 06:38:31 +08:00
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kernel_invariants = {"core", "sysclk", "batch"}
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2016-03-28 08:05:29 +08:00
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2016-03-09 17:12:50 +08:00
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def __init__(self, dmgr, sysclk, core_device="core"):
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self.core = dmgr.get(core_device)
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self.sysclk = sysclk
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2015-05-09 14:47:40 +08:00
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self.batch = _BatchContextManager(self)
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2015-05-08 22:17:06 +08:00
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@kernel
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2016-03-09 17:12:50 +08:00
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def dds_batch_enter(self):
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2015-05-08 22:17:06 +08:00
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"""Starts a DDS command batch. All DDS commands are buffered
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2015-08-08 23:05:00 +08:00
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after this call, until ``batch_exit`` is called.
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2016-06-12 13:05:54 +08:00
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The time of execution of the DDS commands is the time cursor position
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when the batch is entered."""
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2015-08-11 00:25:48 +08:00
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dds_batch_enter(now_mu())
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2015-05-08 22:17:06 +08:00
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@kernel
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2016-03-09 17:12:50 +08:00
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def dds_batch_exit(self):
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2015-05-08 22:17:06 +08:00
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"""Ends a DDS command batch. All buffered DDS commands are issued
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2015-08-08 23:05:00 +08:00
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on the bus."""
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2015-08-11 00:25:48 +08:00
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dds_batch_exit()
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2015-05-08 22:17:06 +08:00
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2015-07-14 04:08:20 +08:00
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class _DDSGeneric:
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2016-03-09 17:12:50 +08:00
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"""Core device Direct Digital Synthesis (DDS) channel driver.
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2014-09-30 17:38:52 +08:00
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2015-05-08 22:17:06 +08:00
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Controls one DDS channel managed directly by the core device's runtime.
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2014-09-30 17:38:52 +08:00
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2015-07-08 23:22:43 +08:00
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This class should not be used directly, instead, use the chip-specific
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drivers such as ``AD9858`` and ``AD9914``.
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2016-06-12 13:05:54 +08:00
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The time cursor is not modified by any function in this class.
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2016-03-09 17:12:50 +08:00
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:param bus: name of the DDS bus device that this DDS is connected to.
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2015-05-08 14:44:39 +08:00
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:param channel: channel number of the DDS device to control.
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2014-09-30 17:38:52 +08:00
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"""
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2016-03-28 08:05:29 +08:00
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2016-04-07 06:38:31 +08:00
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kernel_invariants = {
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2016-03-29 16:19:03 +08:00
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"core", "core_dds", "bus_channel", "channel", "pow_width"
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2016-03-28 08:05:29 +08:00
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}
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2016-03-10 00:23:02 +08:00
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def __init__(self, dmgr, bus_channel, channel, core_dds_device="core_dds"):
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2016-03-09 17:12:50 +08:00
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self.core_dds = dmgr.get(core_dds_device)
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self.core = self.core_dds.core
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self.bus_channel = bus_channel
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2015-07-14 04:08:20 +08:00
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self.channel = channel
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2015-05-08 14:44:39 +08:00
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self.phase_mode = PHASE_MODE_CONTINUOUS
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2014-05-31 00:20:13 +08:00
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2016-03-29 05:25:40 +08:00
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@portable(flags=["fast-math"])
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2014-10-13 17:05:35 +08:00
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def frequency_to_ftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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2016-03-09 17:12:50 +08:00
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return round(int(2, width=64)**32*frequency/self.core_dds.sysclk)
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2014-10-13 17:05:35 +08:00
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2016-03-29 05:25:40 +08:00
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@portable(flags=["fast-math"])
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2014-10-13 17:05:35 +08:00
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def ftw_to_frequency(self, ftw):
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"""Returns the frequency corresponding to the given frequency tuning
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word.
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"""
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2016-03-09 17:12:50 +08:00
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return ftw*self.core_dds.sysclk/int(2, width=64)**32
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2014-10-13 17:05:35 +08:00
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2016-03-29 05:25:40 +08:00
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@portable(flags=["fast-math"])
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2015-07-02 04:22:53 +08:00
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def turns_to_pow(self, turns):
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"""Returns the phase offset word corresponding to the given phase
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in turns."""
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2015-07-08 23:22:43 +08:00
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return round(turns*2**self.pow_width)
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2015-07-02 04:22:53 +08:00
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2016-03-29 05:25:40 +08:00
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@portable(flags=["fast-math"])
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2015-07-02 04:22:53 +08:00
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def pow_to_turns(self, pow):
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"""Returns the phase in turns corresponding to the given phase offset
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word."""
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2015-07-08 23:22:43 +08:00
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return pow/2**self.pow_width
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2015-07-02 04:22:53 +08:00
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2016-06-04 11:34:20 +08:00
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@portable(flags=["fast-math"])
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2015-09-06 03:14:01 +08:00
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def amplitude_to_asf(self, amplitude):
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"""Returns amplitude scale factor corresponding to given amplitude."""
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return round(amplitude*0x0fff)
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2016-06-04 11:34:20 +08:00
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@portable(flags=["fast-math"])
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2015-09-06 03:14:01 +08:00
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def asf_to_amplitude(self, asf):
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"""Returns the amplitude corresponding to the given amplitude scale
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factor."""
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2016-06-04 11:01:59 +08:00
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return asf/0x0fff
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2015-09-06 03:14:01 +08:00
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2015-05-08 14:44:39 +08:00
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@kernel
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def init(self):
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2015-05-09 17:11:34 +08:00
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"""Resets and initializes the DDS channel.
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2016-03-29 11:10:53 +08:00
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This needs to be done for each DDS channel before it can be used, and
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it is recommended to use the startup kernel for this.
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This function cannot be used in a batch; the correct way of
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initializing multiple DDS channels is to call this function
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2016-03-29 12:01:22 +08:00
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sequentially with a delay between the calls. 2ms provides a good
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2016-03-29 11:10:53 +08:00
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timing margin."""
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2016-03-09 17:12:50 +08:00
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dds_init(now_mu(), self.bus_channel, self.channel)
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2015-05-08 14:44:39 +08:00
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2014-09-05 12:03:22 +08:00
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@kernel
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2014-11-21 04:32:56 +08:00
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def set_phase_mode(self, phase_mode):
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"""Sets the phase mode of the DDS channel. Supported phase modes are:
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* ``PHASE_MODE_CONTINUOUS``: the phase accumulator is unchanged when
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switching frequencies. The DDS phase is the sum of the phase
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accumulator and the phase offset. The only discrete jumps in the
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DDS output phase come from changes to the phase offset.
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* ``PHASE_MODE_ABSOLUTE``: the phase accumulator is reset when
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switching frequencies. Thus, the phase of the DDS at the time of
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the frequency change is equal to the phase offset.
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* ``PHASE_MODE_TRACKING``: when switching frequencies, the phase
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accumulator is set to the value it would have if the DDS had been
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running at the specified frequency since the start of the
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experiment.
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"""
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self.phase_mode = phase_mode
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@kernel
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2015-09-06 03:14:01 +08:00
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def set_mu(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT,
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amplitude=0x0fff):
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2015-05-08 14:44:39 +08:00
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"""Sets the DDS channel to the specified frequency and phase.
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2014-11-21 04:32:56 +08:00
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2015-07-08 23:22:43 +08:00
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This uses machine units (FTW and POW). The frequency tuning word width
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is 32, whereas the phase offset word width depends on the type of DDS
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2015-09-06 03:14:01 +08:00
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chip and can be retrieved via the ``pow_width`` attribute. The amplitude
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width is 12.
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2015-07-02 04:22:53 +08:00
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2016-06-12 13:05:54 +08:00
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The "frequency update" pulse is sent to the DDS with a fixed latency
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with respect to the current position of the time cursor.
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2014-11-21 04:32:56 +08:00
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:param frequency: frequency to generate.
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2015-06-26 18:05:11 +08:00
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:param phase: adds an offset, in turns, to the phase.
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2014-11-21 04:32:56 +08:00
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:param phase_mode: if specified, overrides the default phase mode set
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by ``set_phase_mode`` for this call.
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2014-09-30 17:38:52 +08:00
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"""
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2015-06-26 18:05:11 +08:00
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if phase_mode == _PHASE_MODE_DEFAULT:
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2015-05-08 14:44:39 +08:00
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phase_mode = self.phase_mode
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2016-03-09 17:12:50 +08:00
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dds_set(now_mu(), self.bus_channel, self.channel,
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frequency, phase, phase_mode, amplitude)
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2014-09-09 22:00:51 +08:00
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2015-07-02 04:22:53 +08:00
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@kernel
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2015-09-06 03:14:01 +08:00
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def set(self, frequency, phase=0.0, phase_mode=_PHASE_MODE_DEFAULT,
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amplitude=1.0):
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2015-07-02 04:22:53 +08:00
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"""Like ``set_mu``, but uses Hz and turns."""
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self.set_mu(self.frequency_to_ftw(frequency),
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2015-09-06 03:14:01 +08:00
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self.turns_to_pow(phase), phase_mode,
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self.amplitude_to_asf(amplitude))
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2015-07-08 23:22:43 +08:00
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class AD9858(_DDSGeneric):
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"""Driver for AD9858 DDS chips. See ``_DDSGeneric`` for a description
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of the functionality."""
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pow_width = 14
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class AD9914(_DDSGeneric):
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"""Driver for AD9914 DDS chips. See ``_DDSGeneric`` for a description
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of the functionality."""
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pow_width = 16
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2016-08-15 17:45:18 +08:00
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@kernel
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def init_sync(self, sync_delay=0):
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"""Resets and initializes the DDS channel as well as configures
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the AD9914 DDS for synchronisation. The synchronisation procedure
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follows the steps outlined in the AN-1254 application note.
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This needs to be done for each DDS channel before it can be used, and
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it is recommended to use the startup kernel for this.
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This function cannot be used in a batch; the correct way of
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initializing multiple DDS channels is to call this function
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sequentially with a delay between the calls. 10ms provides a good
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timing margin.
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:param sync_delay: integer from 0 to 0x3f that sets value of
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SYNC_OUT (bits 3-5) and SYNC_IN (bits 0-2) delay ADJ bits."""
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dds_init_sync(now_mu(), self.bus_channel, self.channel, sync_delay)
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