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Introduce compiler and device modules

This commit is contained in:
Sebastien Bourdeauducq 2014-05-30 18:20:13 +02:00
parent 18ef03c545
commit c769bdab9b
8 changed files with 70 additions and 19 deletions

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@ -1,6 +1,7 @@
import inspect, textwrap, ast, types
from artiq import units, unparse
from artiq.language import units
from artiq.compiler import unparse
def find_kernel_body(node):
while True:
@ -196,11 +197,8 @@ def collapse(stmts):
stmts[offset+location:offset+location+1] = new_stmts
offset += len(new_stmts) - 1
if __name__ == "__main__":
import collapse_test
kernel = collapse_test.collapse_test
node = ast.parse(textwrap.dedent(inspect.getsource(kernel)))
def transform(k_function, k_args, k_kwargs):
node = ast.parse(textwrap.dedent(inspect.getsource(k_function)))
node = find_kernel_body(node)
explicit_delays(node)

5
artiq/devices/core.py Normal file
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@ -0,0 +1,5 @@
from artiq.compiler.transform import transform
class Core:
def run(self, k_function, *k_args, **k_kwargs):
transform(k_function, k_args, k_kwargs)

25
artiq/devices/core_dds.py Normal file
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@ -0,0 +1,25 @@
from artiq.language.experiment import *
from artiq.language.units import *
class DDS:
def __init__(self, core, reg_channel, rtio_channel, latency=0*ps, phase_mode="continuous"):
self.core = core
self.reg_channel = reg_channel
self.rtio_channel = rtio_channel
self.latency = latency
self.phase_mode = phase_mode
self._previous_frequency = 0*MHz
kernel_attr_ro = {"reg_channel", "rtio_channel", "latency", "phase_mode"}
kernel_attr = {"_previous_frequency"}
@kernel
def pulse(self, frequency, duration):
if self._previous_frequency != frequency:
self.core.syscall("rtio_sync", self.rtio_channel) # wait until output is off
self.core.syscall("dds_program", self.reg_channel, frequency)
self._previous_frequency = frequency
self.core.syscall("rtio_set", now()-self.latency, self.rtio_channel, 1)
delay(duration)
self.core.syscall("rtio_set", now()-self.latency, self.rtio_channel, 0)

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@ -1,6 +1,9 @@
import itertools
class Experiment:
channels = ""
parameters = ""
def __init__(self, *args, **kwargs):
channels = self.channels.split()
parameters = self.parameters.split()
@ -24,9 +27,9 @@ class Experiment:
def kernel(arg):
if isinstance(arg, str):
def real_decorator(function):
def real_decorator(k_function):
def run_on_core(exp, *k_args, **k_kwargs):
getattr(exp, arg).run(function, exp, *k_args, **k_kwargs)
getattr(exp, arg).run(k_function, exp, *k_args, **k_kwargs)
return run_on_core
return real_decorator
else:

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@ -4,8 +4,8 @@ from artiq.language import units
from artiq.sim import time
class Core:
def run(self, function, *args, **kwargs):
return function(*args, **kwargs)
def run(self, k_function, *k_args, **k_kwargs):
return k_function(*k_args, **k_kwargs)
class Input:
def __init__(self, name, prng_seed=None, wait_max=20, count_max=100, wait_min=0, count_min=0):

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@ -1,9 +0,0 @@
def collapse_test():
for i in range(3):
with parallel:
with sequential:
pulse("a", 100*MHz, 20*us)
pulse("b", 100*MHz, 10*us)
with sequential:
pulse("A", 100*MHz, 10*us)
pulse("B", 100*MHz, 10*us)

29
examples/compiler_test.py Normal file
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@ -0,0 +1,29 @@
from artiq.language.units import *
from artiq.language.experiment import *
class CompilerTest(Experiment):
channels = "core a b A B"
@kernel
def run():
for i in range(3):
with parallel:
with sequential:
self.a.pulse(100*MHz, 20*us)
self.b.pulse(100*MHz, 10*us)
with sequential:
self.A.pulse(100*MHz, 10*us)
self.B.pulse(100*MHz, 10*us)
if __name__ == "__main__":
from artiq.devices import core, core_dds
coredev = core.Core()
exp = CompilerTest(
core=coredev,
a=core_dds.DDS(coredev, 0, 0),
b=core_dds.DDS(coredev, 1, 1),
A=core_dds.DDS(coredev, 2, 2),
B=core_dds.DDS(coredev, 3, 3)
)
exp.run()