forked from M-Labs/artiq
embedding: s/kernel_constant_attributes/kernel_invariants/g
Requested in #359.
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parent
32102bc25f
commit
9cc9e8b276
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@ -137,9 +137,9 @@ class ASTSynthesizer:
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instance_type = types.TInstance("{}.{}".format(typ.__module__, typ.__qualname__),
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OrderedDict())
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instance_type.attributes['__objectid__'] = builtins.TInt32()
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if hasattr(typ, 'kernel_constant_attributes'):
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assert isinstance(typ.kernel_constant_attributes, set)
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instance_type.constant_attributes = typ.kernel_constant_attributes
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if hasattr(typ, 'kernel_invariants'):
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assert isinstance(typ.kernel_invariants, set)
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instance_type.constant_attributes = typ.kernel_invariants
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constructor_type = types.TConstructor(instance_type)
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constructor_type.attributes['__objectid__'] = builtins.TInt32()
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@ -59,7 +59,7 @@ class Core:
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:param comm_device: name of the device used for communications.
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"""
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kernel_constant_attributes = {
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kernel_invariants = {
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"core", "ref_period", "coarse_ref_period", "ref_multiplier",
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"external_clock",
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}
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@ -29,7 +29,7 @@ def dds_batch_exit() -> TNone:
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class _BatchContextManager:
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kernel_constant_attributes = {"core", "core_dds"}
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kernel_invariants = {"core", "core_dds"}
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def __init__(self, core_dds):
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self.core_dds = core_dds
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@ -53,7 +53,7 @@ class CoreDDS:
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phase-locked multiple of the RTIO clock.
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"""
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kernel_constant_attributes = {"core", "sysclk", "batch"}
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kernel_invariants = {"core", "sysclk", "batch"}
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def __init__(self, dmgr, sysclk, core_device="core"):
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self.core = dmgr.get(core_device)
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@ -88,7 +88,7 @@ class _DDSGeneric:
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:param channel: channel number of the DDS device to control.
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"""
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kernel_constant_attributes = {
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kernel_invariants = {
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"core", "core_dds", "bus_channel", "channel", "pow_width"
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}
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@ -10,7 +10,7 @@ class TTLOut:
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:param channel: channel number
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"""
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kernel_constant_attributes = {"core", "channel"}
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kernel_invariants = {"core", "channel"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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@ -84,7 +84,7 @@ class TTLInOut:
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:param channel: channel number
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"""
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kernel_constant_attributes = {"core", "channel"}
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kernel_invariants = {"core", "channel"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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@ -236,7 +236,7 @@ class TTLClockGen:
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:param channel: channel number
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"""
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kernel_constant_attributes = {"core", "channel", "acc_width"}
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kernel_invariants = {"core", "channel", "acc_width"}
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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@ -83,7 +83,7 @@ class ClockGeneratorLoopback(EnvExperiment):
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class PulseRate(EnvExperiment):
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kernel_constant_attributes = {"core", "ttl_out"}
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kernel_invariants = {"core", "ttl_out"}
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def build(self):
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self.setattr_device("core")
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@ -107,7 +107,7 @@ class PulseRate(EnvExperiment):
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class PulseRateDDS(EnvExperiment):
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kernel_constant_attributes = {"core", "core_dds", "dds0", "dds1"}
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kernel_invariants = {"core", "core_dds", "dds0", "dds1"}
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def build(self):
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self.setattr_device("core")
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@ -5,7 +5,7 @@ from artiq.language.core import *
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from artiq.language.types import *
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class c:
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kernel_constant_attributes = {'a'}
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kernel_invariants = {'a'}
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def __init__(self):
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self.a = 1
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