Astro cae02947bc zynq::eth: remove all memory barriers ... They were not the solution.		2019-11-10 23:52:55 +01:00
..
ddr	zynq::ddr: fix DDR 3x/2x setup, print clocks	2019-11-07 00:13:50 +01:00
eth	zynq::eth: remove all memory barriers	2019-11-10 23:52:55 +01:00
uart	Revert "zynq: replace unnecessary slcr::unlocked with new"	2019-11-07 00:13:50 +01:00
axi_gp.rs	add zynq::axi_gp	2019-10-19 01:46:43 +02:00
axi_hp.rs	add zynq::axi_hp	2019-10-18 23:46:00 +02:00
clocks.rs	zynq::clocks: unlock slcr in enable_io()	2019-11-07 00:13:50 +01:00
mod.rs	move slcr, clocks, uart, eth into src/zynq/	2019-10-21 22:19:03 +02:00
slcr.rs	zynq::slcr::unlocked: fix comment	2019-11-07 00:13:50 +01:00