Astro 5c62716a99 zynq::eth: switch rx and tx descriptor words to vcell ... vcell can be initialized cleanly.		2019-10-31 03:15:13 +01:00
..
ddr	zynq::ddr: optimize memtest	2019-10-31 01:32:45 +01:00
eth	zynq::eth: switch rx and tx descriptor words to vcell	2019-10-31 03:15:13 +01:00
uart	move slcr, clocks, uart, eth into src/zynq/	2019-10-21 22:19:03 +02:00
axi_gp.rs	add zynq::axi_gp	2019-10-19 01:46:43 +02:00
axi_hp.rs	add zynq::axi_hp	2019-10-18 23:46:00 +02:00
clocks.rs	zynq::ddr: parameters	2019-10-27 20:38:06 +01:00
mod.rs	move slcr, clocks, uart, eth into src/zynq/	2019-10-21 22:19:03 +02:00
slcr.rs	zynq::slcr: doc, fix	2019-10-25 23:18:18 +02:00