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zc706
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Commit Graph

69 Commits (0adb0d5c51d0c483fc5e7845d0a26e8159c40e68)

Author SHA1 Message Date
Astro 0adb0d5c51 zynq::flash: remove post-WRDI check 2019-12-16 00:49:29 +01:00
Astro dd0fe054d7 zynq::flash: add working erase(), add barely working program() 2019-12-16 00:48:39 +01:00
Astro 1dbb358a4c zynq::flash::spi_flash_register: doc, add BA 2019-12-16 00:46:53 +01:00
Astro b94afa1581 zynq::flash: add read_reg_until() 2019-12-15 23:56:16 +01:00
Astro 0d1cf04a34 zynq::flash: split into mod transfer 2019-12-15 19:28:55 +01:00
Astro 8a9dde6119 zynq::flash: add consts 2019-12-14 01:57:51 +01:00
Astro 5268839467 zynq::flash: add write_enabled() 2019-12-14 01:56:49 +01:00
Astro 0b9a150255 zynq::flash: abstract SpiFlashRegister 2019-12-14 01:55:17 +01:00
Astro 2d1c8e1f4f zynq::flash: fix txd[123] alignment 2019-12-14 01:07:15 +01:00
Astro e1068af948 zynq::flash: add rdsr1() 2019-12-12 01:02:09 +01:00
Astro 3b3b5dc7c1 zynq::flash: add support for writing 1/2/3-byte words 2019-12-12 00:17:34 +01:00
Astro 70d56d2b28 zynq::flash: doc 2019-12-12 00:13:02 +01:00
Astro b346ea8297 zynq::flash: fix INST_RDCR 2019-12-12 00:11:42 +01:00
Astro e9b80eaef9 zynq::flash: don't send excess data, fixes, refactorings 2019-12-10 02:50:44 +01:00
Astro 0823a74164 zynq::flash: fix rx_thres register 2019-12-10 02:46:25 +01:00
Astro aab82f6843 zynq::flash: enable big endian mode 2019-12-10 02:45:05 +01:00
Astro f3676c945a zynq::flash: flush after instruction 2019-12-07 02:48:55 +01:00
Astro 1e465250f5 zynq::flash: enable/disable spi for every transfer 2019-12-07 02:11:50 +01:00
Astro e37659e4b3 zynq::flash: refactor 2019-12-05 01:18:52 +01:00
Astro 45cc271735 zynq::flash: fix + refactor 2019-12-05 00:05:34 +01:00
Astro cfaa1213e2 zynq::flash: add more initialization 2019-12-03 02:41:49 +01:00
Astro 7107244a6e zynq::flash: start implementing Manual mode 2019-11-30 02:48:39 +01:00
Astro dd3ad3be67 zynq::flash: implement stopping LinearAddressing mode 2019-11-29 23:48:08 +01:00
Astro a8a7f11990 zynq::flash: configure quad i/o fast read mode 2019-11-29 23:37:54 +01:00
Astro 78caca1f04 zynq::flash: setup additional signals 2019-11-28 03:22:26 +01:00
Astro 5642feb824 zynq::flash: add missing config bits to enable addressing mode 2019-11-28 03:02:51 +01:00
Astro a199a5dc7d zynq::flash: add more setup 2019-11-23 01:59:24 +01:00
Astro 3180f1c3f7 zynq::flash: begin driver implementation 2019-11-21 00:14:09 +01:00
Astro 8037042040 zynq::slcr: implement boot_mode bits 2019-11-20 21:31:54 +01:00
Astro ef6d0ff3f1 boot: reset core1 before start 2019-11-18 00:38:03 +01:00
Astro 49901d1b8a boot: prepare core1 bootup 2019-11-15 23:59:01 +01:00
Björn Stein 4a1d0fc0c3 zynq::mpcore: add register definitions 2019-11-14 02:11:58 +01:00
Astro 3279aab961 main: refactor into abort, panic, ram 2019-11-11 02:46:18 +01:00
Astro 92c274348f zynq::eth: enable checksum offload 2019-11-11 01:42:41 +01:00
Astro 3eb7fce572 delint 2019-11-11 01:42:38 +01:00
Astro 3496755406 update rust + smoltcp 2019-11-11 00:28:46 +01:00
Astro 959bf8a245 zynq::eth: don't check_link_change if link already established 2019-11-11 00:08:48 +01:00
Astro 4d3b2ac7e5 zynq::ddr: use different data_bus_width for targets 
DDR still works only on the zc706, not on the cora z7-10.
 2019-11-11 00:06:35 +01:00
Astro cae02947bc zynq::eth: remove all memory barriers 
They were not the solution.
 2019-11-10 23:52:55 +01:00
Astro afd96bd887 zynq::clocks: unlock slcr in enable_io() 2019-11-07 00:13:50 +01:00
Astro 261455877d zynq::ddr: fix DDR 3x/2x setup, print clocks 2019-11-07 00:13:50 +01:00
Astro ff96bf903b zynq::ddr: only enable_ddr if no clock yet 
that's only an issue for the cora z7
 2019-11-07 00:13:50 +01:00
Astro d2df5652d0 Revert "zynq: replace unnecessary slcr::unlocked with new" 
This reverts commit 6bee1f44f4.
 2019-11-07 00:13:50 +01:00
Astro eb56dda44f zynq::slcr::unlocked: fix comment 2019-11-07 00:13:50 +01:00
Astro 74c43b3477 zynq::eth::tx: clear entry.word1 for each packet 2019-11-04 02:31:40 +01:00
Astro 99a00e019b zynq::eth: implement phy::extended_status, set clock for link speed 2019-11-04 02:30:00 +01:00
Astro 961e2e1dd0 zynq::{ddr, eth}: fix clock divisor calculation 
off-by-one, didn't change behavior.
 2019-11-03 02:23:16 +01:00
Astro 04e816d99e zynq::slcr: fix a bitfield index 
that didn't solve our problems.
 2019-11-03 02:01:42 +01:00
Astro 6bee1f44f4 zynq: replace unnecessary slcr::unlocked with new 2019-10-31 20:48:07 +01:00
Astro 5c62716a99 zynq::eth: switch rx and tx descriptor words to vcell 
vcell can be initialized cleanly.
 2019-10-31 03:15:13 +01:00