a8ac943190
Cleanup and Update Modification Date
2023-11-28 11:44:52 +08:00
2612acc9f7
Scripts: Comment Filed is included in the BOM
2023-11-28 10:42:26 +08:00
06a00befeb
3D: Update 3D models of KIrdy LD Adapter
2023-11-28 10:42:26 +08:00
1b7940871b
sch, pcb: Add 12V & Mounting holes to MCU EXT HDR
2023-11-28 10:42:20 +08:00
83506fd3c6
sch, pcb: add tantalum C0G Caps for 8V out LT3045
2023-11-27 17:37:52 +08:00
f24f037348
sch, pcb: Change kirdy LD adpter connectors
...
- Add two extra mounting holes for kirdy LD adapter
- Update kirdy LD adapter 3D model
- Update the PCB layout accordingly
2023-11-27 17:37:52 +08:00
95494ee031
sch, pcb: Add LPF and Buffer for TEC VREF
2023-11-27 17:37:52 +08:00
e7a7eee202
sch, pcb: Remove X7R, X5R at input LT304x
...
- Reduce the number of Tantalum Capacitor Used
- Replace some non critical ones with Electrolytic Caps
2023-11-27 17:37:52 +08:00
f29c460e72
Add: Footprints and Step Model for Caps
...
- SMD ELEC: 865080345012
- SMD C0G Ceramic GRMJN65C1H104JE01J
2023-11-27 17:37:52 +08:00
5f7743698e
pcb: Add reference designators for connectors, SWs
...
- SMA Connector, USB Type C, Power Jack, RJ45
- MCU Programming Headers and Boot 0 Headers
- Termination Resistor SW, Modulation Depth SW
2023-11-27 17:37:52 +08:00
43903708c3
sch, pcb: Replace FB of -6V +15V LDO with inductor
...
- Build a Pi LPF on the input side
2023-11-27 17:37:52 +08:00
24637b4216
sch, pcb: Add alternate footprint for LTC6655 Vref
2023-11-27 17:37:52 +08:00
2cbab29c4e
sch, pcb: Add LEDs and TPs to Critical Power Rails
2023-11-27 17:37:52 +08:00
c59eccaa7d
sch, pcb: add 0R for TEC Vref Ouput
...
- For debugging if needed
2023-11-27 17:37:52 +08:00
db54e6cfa8
sch, pcb:Edit PCB shape for connectors to protrude
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- Connectors now protrude the front panel
- Align the connectors by the outline generated from 3D Model
- Update the front panel symbol to include the two mounting holes
2023-11-27 17:37:52 +08:00
e0989a61f2
Add Front Panel FreeCAD Assembly
...
- Static Handle
- PCB Brackets
- Kirdy Front Panel Cutout
2023-11-27 17:37:47 +08:00
13a90dd642
3D_Model: Update 204-121ST
2023-11-21 11:46:48 +08:00
b901f84d0a
sch, pcb: Add PWR, POE_PWR netclasses
2023-11-21 11:46:46 +08:00
20198f5eab
drc: Check PWR nets clearance on pri and sec sides
...
- Pri: PoE PWR nets
- Sec: PWR nets like GND, 3V3 etc
2023-11-21 11:46:39 +08:00
47a30da9b1
Port front panel markings design to Kicad
...
- Front panel text markings can now be modified with Kicad
2023-11-17 15:57:55 +08:00
de7c27c21f
sch, pcb: Add mounting holes for Kirdy LD Adapter
2023-11-17 15:42:43 +08:00
41db8612c0
pcb: relocate switches for better accessibility
...
- modulation depth SW and termination SW are relocated
2023-11-15 17:12:05 +08:00
de3e034c7a
Add Front Panel, Kirdy LD Adapter 3D models
...
- Update sch, pcb, sym lib, footrprint lib
- Position of Kirdy LD Adapter is relocated so that it is symmetric
2023-11-15 17:11:51 +08:00
9f3793c8fb
pcb: Add 3D Models
2023-11-10 17:32:29 +08:00
0b99a8f119
sch, pcb: Correct MFR/PN and optimize BOM
2023-11-10 15:18:22 +08:00
7c72afe55f
Remove old production files
2023-11-10 15:18:21 +08:00
cd679cf0da
sch: Update Title Block Info
...
- rev0.3 -> rev0_3
- Correct the title of each schematics
- Update the modified time
2023-11-10 15:18:21 +08:00
35da9f8c58
scripts: Add scripts to generate production files
...
- The following files can be generated from the script.
1. Zipped(Gerber, Drill, Drill Map)
2. Bom,
3. Component Placement
4. Schematics PDF
5. Step Files
2023-11-10 15:18:17 +08:00
5ad5914748
sch, pcb: exclude MHs and soldering JP from BOM
2023-11-09 15:24:07 +08:00
a30ac45c5f
pcb: Remove "designed by" silkscreen
2023-11-08 11:53:18 +08:00
13b5f661c5
pcb: Fix TEC Polarity Connections to Header
...
- Fix Issue #27
2023-11-08 11:53:07 +08:00
7aa84d4d23
sch: Fix incorrect TEC polarity in thermostat
...
- Fix Issue #27
2023-11-08 11:52:51 +08:00
7b5df5150f
thermostat: Fix wrong P/N in TEC Current Sense Res
...
- Fix Issue #26
2023-11-08 11:13:38 +08:00
2a6ad78f51
pcb: Finish Layout for rev0_3
...
- Assign MFR_PN for all Components
- schematics changes:
- drivestage: Add Switch to optionally enable Modulation Signal Termination
- Add alternate Precision Power Resistor
- Modify the RC network values at TIA LPF Output
- MCU: Add Redundant 2.54mm pitch Programming Header
- thermostat: Duplicate the power filter network for alternate Temperature ADC
2023-11-02 15:24:26 +08:00
352f8c075d
footprint: Add TL082Hx TI SOIC-8 footprint
2023-10-31 11:02:47 +08:00
0c3c8a3fd1
sch: Update power related flags and nets symbols
...
- Update the symbol from the kicad 7 built-in library
- Remove ERC warnings
2023-10-31 10:29:43 +08:00
fc02f24131
sch: correct POE_VC* pins name case
...
- PoE_VC* -> POE_VC*
2023-10-31 10:23:07 +08:00
caf69e4a0f
symbol: correct RJ45 VC output pin type
...
- from power input to power output
2023-10-31 10:21:18 +08:00
b0525c4d74
symbol: AD7172-4 sets DNC pin to unconnected type
2023-10-30 17:40:40 +08:00
1f9b4e9900
sch: fix Temperature ADC SPI Connections
...
- Fix Issue #25
2023-10-30 17:32:43 +08:00
395e104575
sch: add lpf at TEC_VSEN Buffer Output
2023-10-30 17:29:44 +08:00
86f5addbad
sch: Correct typos in TEC_~{SHDN} ports
2023-10-30 12:17:26 +08:00
f66625e431
sch: Add redundant 2.54mm SWD Header
2023-10-27 17:45:39 +08:00
fcae5b785e
sch: Correct SWD Header MF/PN and Update Footprint
...
- Use Adafuit 4048 Mini SWD Headers
- Silkscreen is modified to indicate orientation of the header
2023-10-27 17:42:46 +08:00
89dab2b553
sch: Change PoE RJ45 Jack and change PM1202 Symbol
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- Use the same PoE RJ45 as sinara-hw thermostat
- Add PM1202 Power input pins (VB+, VB-)
- Remove PoE softstart circuit as PM1202 has inrush current limiting
- Add Pi Filter at the output of PM1202
2023-10-27 15:33:39 +08:00
929ff58706
sch: Set DNP for DNP components
2023-10-25 17:36:20 +08:00
57e013c9c5
sch: Support Temp ADC in alternate footprint
...
- Issue #12
- Add Alternate AD7172-4BCPZ circuitry, symbol, footprint and 3D model
2023-10-25 17:36:20 +08:00
d2c80458aa
sch: Do not pass MCU RST to ETH
...
- D3 -> DNP
2023-10-25 17:36:20 +08:00
f732b9944a
sch: Fix Issue #14
2023-10-25 17:36:20 +08:00
f1bda76636
sch: correct ethernet phy sigs connections to ESD
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- Pull up eth signals with 100R instead of pull down
2023-10-25 17:36:20 +08:00
