sch, pcb: Add PWR, POE_PWR netclasses

dsupply.kicad_sch

@@ -2164,6 +2164,11 @@
     (uuid b9016901-3dc8-46a6-bfc5-d7a28dd97dba)
   )
 
+  (label "+12V_Barrel_Jack" (at 199.136 31.75 0) (fields_autoplaced)
+    (effects (font (size 1.27 1.27)) (justify left bottom))
+    (uuid a514e706-0748-4059-8680-babd922e05e7)
+  )
+
   (global_label "12Vin" (shape passive) (at 290.83 66.04 0) (fields_autoplaced)
     (effects (font (size 1.27 1.27)) (justify left))
     (uuid ddeb5a88-7444-4199-858d-84b69dbaabae)

eth.kicad_sch

@@ -3826,8 +3826,8 @@
     (pin "5" (uuid aeb2759d-1fd8-43ce-8951-9d9386ce271c))
     (pin "6" (uuid 836a350b-8422-422a-88d3-a0cd8eddee47))
     (pin "7" (uuid 931473ba-af41-4e36-b6c9-9a3fb1032bbd))
-    (pin "8" (uuid 5214f442-9c8d-426e-a560-c92096489a12))
-    (pin "8" (uuid 5214f442-9c8d-426e-a560-c92096489a12))
+    (pin "8" (uuid 5214f442-9c8d-426e-a560-c92096489a13))
+    (pin "8" (uuid 5214f442-9c8d-426e-a560-c92096489a13))
     (pin "9" (uuid 8bc5a6f7-ced1-468f-aa5d-6d53092fa02a))
     (instances
       (project "kirdy"

kirdy.kicad_pro

@@ -454,6 +454,40 @@
         "via_diameter": 0.8,
         "via_drill": 0.4,
         "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.0889,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "POE_PWR",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.0889,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "PWR",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
       }
     ],
     "meta": {
@@ -461,7 +495,28 @@
     },
     "net_colors": null,
     "netclass_assignments": null,
-    "netclass_patterns": []
+    "netclass_patterns": [
+      {
+        "netclass": "POE_PWR",
+        "pattern": "/*/POE_VC*"
+      },
+      {
+        "netclass": "PWR",
+        "pattern": "+*"
+      },
+      {
+        "netclass": "PWR",
+        "pattern": "-*"
+      },
+      {
+        "netclass": "PWR",
+        "pattern": "GND"
+      },
+      {
+        "netclass": "PWR",
+        "pattern": "/*/+*"
+      }
+    ]
   },
   "pcbnew": {
     "last_paths": {