a2cb5ce624sch, pcb: Add TDAC_VFB. Change 2u2 PMLCAP P/N - Connect TDAC voltage output through a RC LPF to MCU PC0(ADC123_IN10) - 2u2 PMLCAP P/N is changed to 16V version instead of 35V for lower costlinuswck2023-12-15 10:30:02 +0800
7ac52b7a1bPCB: Correct Y169010R0000T9L Footprint - Add more space between the pin holes and resistor bodylinuswck2023-12-13 15:16:48 +0800
901f394ab3Correct graphical mistakes in LTC3261 symbol - no functional changeslinuswck2023-12-13 12:18:14 +0800
ef732cf36bsch, pcb: correct polarity of LT3094xMSE C_Setlinuswck2023-12-13 11:48:17 +0800
6cd368a203sch: Add SMA Jack to Plug Cable to BOM - Internal SMA cable connecting LD adapter and Front Panellinuswck2023-12-13 11:26:00 +0800
eaea402d9cAdd copper plate to LD Adapter 3D modellinuswck2023-12-12 13:05:21 +0800
9e1f359d78flake: Generate prod files with flake.nix - Generate production files with nix build .linuswck2023-12-12 11:43:39 +0800
a0c1ca1c58pcb: Update clearance rules for JLCPCB manufacturing - No layout is changed. Only copper clearance and width are modified.linuswck2023-12-11 11:03:47 +0800
6d686d7170sch: Place Y169010R Power Resistor - cannot find purchasable PDY10R000F Power Resistorlinuswck2023-12-11 11:02:10 +0800
816e273b7asch: Add JLCPCB M3 x 8 Screws PNlinuswck2023-12-11 10:55:50 +0800
b0e798a83esch: Set the mcu 2.54mm Prog HDR to be placedlinuswck2023-12-11 10:54:34 +0800
19a860fbb4sch: Specify AD5680 MFR_PN to be -1 variantlinuswck2023-12-11 10:52:11 +0800
430a67dda4pcb: Update Front Panel 3D Modellinuswck2023-12-11 10:51:06 +0800
71f2a39713Add Front Panel Mechanical Design and Drawings - Complete the Assembly in FreeCAD - Add Technical Drawings, Assembly Drawings, 3D model for production - Update text markings on KiCadlinuswck2023-12-11 10:50:29 +0800
3b7fbdb2bepcb: Update PN and properties of symbolslinuswck2023-11-30 16:13:57 +0800
8b3d5d8e44sch: Not to include TPs in BOM. Add prod comments - LTC6655 Vref adds production commentslinuswck2023-11-30 15:59:33 +0800
83bd5e9a03Front Panel: Relocate markings to diff layers - Move the markings to different layers for generating prod docs - Add comments in the drawings pdflinuswck2023-11-30 15:00:54 +0800
08133e5e95sch, pcb: Add TAN Caps to all LT304x SET Pin - Prevent noise due to microphonics to be amplified by internal Amp - Remove the input TAN Caps as LT304x PSRR is very good - Replace TAN Caps in the 12V input side to be ELEC Cap - Save costlinuswck2023-11-29 15:04:31 +0800
74524b70e4Scripts: Grab correct KICAD7_3DMODEL_DIR now - Todo: Use default.nix or flake.nix to setup the pathlinuswck2023-11-29 15:01:30 +0800
13720b3cccReassign Reference Designators for all Symbolslinuswck2023-11-29 10:46:07 +0800
f558f62313sch: Add Mounting Screw Symbol and MFR/PNlinuswck2023-11-28 12:45:19 +0800
a8ac943190Cleanup and Update Modification Datelinuswck2023-11-27 17:40:03 +0800
2612acc9f7Scripts: Comment Filed is included in the BOMlinuswck2023-11-27 11:36:51 +0800
06a00befeb3D: Update 3D models of KIrdy LD Adapterlinuswck2023-11-27 11:36:14 +0800
83506fd3c6sch, pcb: add tantalum C0G Caps for 8V out LT3045linuswck2023-11-24 15:28:48 +0800
f24f037348sch, pcb: Change kirdy LD adpter connectors - Add two extra mounting holes for kirdy LD adapter - Update kirdy LD adapter 3D model - Update the PCB layout accordinglylinuswck2023-11-24 15:18:34 +0800
95494ee031sch, pcb: Add LPF and Buffer for TEC VREFlinuswck2023-11-23 11:41:38 +0800
e7a7eee202sch, pcb: Remove X7R, X5R at input LT304x - Reduce the number of Tantalum Capacitor Used - Replace some non critical ones with Electrolytic Capslinuswck2023-11-22 17:44:09 +0800
f29c460e72Add: Footprints and Step Model for Caps - SMD ELEC: 865080345012 - SMD C0G Ceramic GRMJN65C1H104JE01Jlinuswck2023-11-22 17:41:57 +0800
5f7743698epcb: Add reference designators for connectors, SWs - SMA Connector, USB Type C, Power Jack, RJ45 - MCU Programming Headers and Boot 0 Headers - Termination Resistor SW, Modulation Depth SWlinuswck2023-11-21 16:55:51 +0800
43903708c3sch, pcb: Replace FB of -6V +15V LDO with inductor - Build a Pi LPF on the input sidelinuswck2023-11-21 16:46:22 +0800
24637b4216sch, pcb: Add alternate footprint for LTC6655 Vreflinuswck2023-11-21 15:34:06 +0800
2cbab29c4esch, pcb: Add LEDs and TPs to Critical Power Railslinuswck2023-11-21 13:30:36 +0800
c59eccaa7dsch, pcb: add 0R for TEC Vref Ouput - For debugging if neededlinuswck2023-11-21 10:42:27 +0800
db54e6cfa8sch, pcb:Edit PCB shape for connectors to protrude - Connectors now protrude the front panel - Align the connectors by the outline generated from 3D Model - Update the front panel symbol to include the two mounting holeslinuswck2023-11-20 17:40:23 +0800
e0989a61f2Add Front Panel FreeCAD Assembly - Static Handle - PCB Brackets - Kirdy Front Panel Cutoutlinuswck2023-11-20 17:33:06 +0800
41db8612c0pcb: relocate switches for better accessibility - modulation depth SW and termination SW are relocatedlinuswck2023-11-15 13:33:09 +0800
de3e034c7aAdd Front Panel, Kirdy LD Adapter 3D models - Update sch, pcb, sym lib, footrprint lib - Position of Kirdy LD Adapter is relocated so that it is symmetriclinuswck2023-11-15 11:49:53 +0800
cd679cf0dasch: Update Title Block Info - rev0.3 -> rev0_3 - Correct the title of each schematics - Update the modified timelinuswck2023-11-09 14:32:44 +0800
35da9f8c58scripts: Add scripts to generate production files - The following files can be generated from the script. 1. Zipped(Gerber, Drill, Drill Map) 2. Bom, 3. Component Placement 4. Schematics PDF 5. Step Fileslinuswck2023-11-09 13:19:32 +0800
5ad5914748sch, pcb: exclude MHs and soldering JP from BOMlinuswck2023-11-08 17:14:43 +0800
7b5df5150fthermostat: Fix wrong P/N in TEC Current Sense Res - Fix Issue #26linuswck2023-11-08 11:07:17 +0800
2a6ad78f51pcb: Finish Layout for rev0_3 - Assign MFR_PN for all Components - schematics changes: - drivestage: Add Switch to optionally enable Modulation Signal Termination - Add alternate Precision Power Resistor - Modify the RC network values at TIA LPF Output - MCU: Add Redundant 2.54mm pitch Programming Header - thermostat: Duplicate the power filter network for alternate Temperature ADClinuswck2023-11-01 17:36:15 +0800
352f8c075dfootprint: Add TL082Hx TI SOIC-8 footprintlinuswck2023-10-31 11:02:47 +0800
0c3c8a3fd1sch: Update power related flags and nets symbols - Update the symbol from the kicad 7 built-in library - Remove ERC warningslinuswck2023-10-31 10:29:43 +0800
fc02f24131sch: correct POE_VC* pins name case - PoE_VC* -> POE_VC*linuswck2023-10-31 10:23:07 +0800
caf69e4a0fsymbol: correct RJ45 VC output pin type - from power input to power outputlinuswck2023-10-31 10:18:31 +0800
b0525c4d74symbol: AD7172-4 sets DNC pin to unconnected typelinuswck2023-10-30 17:40:40 +0800
fcae5b785esch: Correct SWD Header MF/PN and Update Footprint - Use Adafuit 4048 Mini SWD Headers - Silkscreen is modified to indicate orientation of the headerlinuswck2023-10-27 17:42:46 +0800
89dab2b553sch: Change PoE RJ45 Jack and change PM1202 Symbol - Use the same PoE RJ45 as sinara-hw thermostat - Add PM1202 Power input pins (VB+, VB-) - Remove PoE softstart circuit as PM1202 has inrush current limiting - Add Pi Filter at the output of PM1202linuswck2023-10-27 15:33:39 +0800
929ff58706sch: Set DNP for DNP componentslinuswck2023-10-25 17:19:03 +0800
57e013c9c5sch: Support Temp ADC in alternate footprint - Issue #12 - Add Alternate AD7172-4BCPZ circuitry, symbol, footprint and 3D modellinuswck2023-10-25 17:01:57 +0800
d2c80458aasch: Do not pass MCU RST to ETH - D3 -> DNPlinuswck2023-10-25 16:59:23 +0800
e62bf3b8d6footprint: Correct PM1202 footprint - enlarge courtyard and silkscreen to reflect the clearance requirement so that it can be fully seated onto the PCBlinuswck2023-10-24 12:30:05 +0800
dfeb1ec6a8sch: LD DAC add parallel Cap to output resistor - Increase the Mod_In Signal Bandwidth - See Issue #22linuswck2023-10-24 10:37:36 +0800
2df59fbce9sch: Use TL082 for PD_Mon TIA and LPF Stagelinuswck2023-10-13 17:27:18 +0800
893f5220c6sch: Add REF3033 for MCU ADC VREFlinuswck2023-10-20 13:29:05 +0800
linuswck
Sebastien Bourdeauducq