 Jack-Zheng
|
66d7d68a55
|
CurrentSense, HSADC: add decoupling caps; Power: add 3.3V output fuse; HSADC: add ESD protection; PCB: add logo
|
2021-07-09 20:18:06 +08:00 |
|
Jack-Zheng
|
3a06817165
|
CurrentSense: connect FAULT signal to MCU
|
2021-07-09 16:07:40 +08:00 |
|
Jack-Zheng
|
191eacdf8c
|
HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout; LVDS&IO: fix name issue
|
2021-07-09 14:36:13 +08:00 |
|
Jack-Zheng
|
2a31c8b3f3
|
PCB: finish LVDS routing
|
2021-06-24 15:43:31 +08:00 |
|
Jack-Zheng
|
6535ff5423
|
LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout
|
2021-06-22 16:34:02 +08:00 |
|
Jack-Zheng
|
b740887ac2
|
HighSpeedADC: fix chip rotation bug, remove SMA connector; all: fix BJT base resistors; Power: remove DC jack; LVDS&IO: replace IDC header with dupont
|
2021-06-21 17:06:36 +08:00 |
|
Jack-Zheng
|
982fefd6b5
|
all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
|
2021-06-21 16:05:17 +08:00 |
|
Jack-Zheng
|
327abdeb24
|
CurrentSensor: fix bugs and replace opamp with current senser
|
2021-06-21 15:10:25 +08:00 |
|
Jack-Zheng
|
9bcc9a229b
|
TestAutomation: replace messy wires with bus
|
2021-06-21 12:10:31 +08:00 |
|
Jack-Zheng
|
45940c1ac8
|
all: finish routing
|
2021-06-18 16:13:42 +08:00 |
|
Jack-Zheng
|
9c10edde19
|
CurrentSensor: add mid point voltage reference; FPGA: fix pinout
|
2021-06-18 14:24:15 +08:00 |
|
Jack-Zheng
|
0cebd6ed2b
|
LVDS: add LVDS ports; all: add LEDs
|
2021-06-18 11:30:16 +08:00 |
|
Jack-Zheng
|
74f4fc201a
|
FPGA: add GPIO and ADC parallel port
|
2021-06-18 10:27:05 +08:00 |
|
Jack-Zheng
|
9a62476f9e
|
MCU: finish connectors
|
2021-06-17 17:33:12 +08:00 |
|
Jack-Zheng
|
4123caa996
|
all: add gitignore; remove redundant files from repo; optimize file name style
|
2021-06-17 15:49:24 +08:00 |