mikelam 900c0e292f add PLL to generate 50MHz clock for ADC		2022-01-09 21:28:03 +08:00
..
ethernet.h	change to STM32F103VFT6; add ADC and SW/LED IO labels; simple testing for 5V GND MOS switch	2021-08-31 17:38:28 +08:00
fpga_bin.h	add PLL to generate 50MHz clock for ADC	2022-01-09 21:28:03 +08:00
fpga.h	multiplexer working	2021-12-31 10:57:11 +08:00
power.h	change to STM32F103VFT6; add ADC and SW/LED IO labels; simple testing for 5V GND MOS switch	2021-08-31 17:38:28 +08:00
test_logic.h	change to STM32F103VFT6; add ADC and SW/LED IO labels; simple testing for 5V GND MOS switch	2021-08-31 17:38:28 +08:00
user_isr.h	add ethernet controller spi driver	2021-07-27 09:58:57 +08:00
user_main.h	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00