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Syrostan-MCU-C
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add PLL to generate 50MHz clock for ADC

master
mikelam 2022-01-09 21:28:03 +08:00
parent fe0d520b28
commit 900c0e292f
3 changed files with 7860 additions and 7843 deletions
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15676
Core/Inc/User/fpga_bin.h
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File diff suppressed because it is too large Load Diff

2
FPGA/pinmap.pcf
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@ -1,5 +1,5 @@
# example.pcf
set_io --warn-no-port HW_CLK R9
set_io --warn-no-port CLK_25M R9
set_io --warn-no-port LED T15
set_io --warn-no-port KEY T16

25
FPGA/top.v
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@ -1,5 +1,5 @@
module top (
HW_CLK,
CLK_25M,
LED,
KEY,
DIO_OUT,
@ -19,7 +19,7 @@ module top (
);
/* I/O */
input HW_CLK;
input CLK_25M;
input KEY;
output LED;
@ -47,12 +47,29 @@ module top (
// assign LED = ~KEY;
/* always */
always @ (posedge HW_CLK) begin
always @ (posedge CLK_25M) begin
counter <= counter + 1;
end
wire CLK_50M;
SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'd0),
.DIVF(7'd1),
.DIVQ(3'd0), //12MHz * (DIVF+1) / 2^DIVQ / (DIVR+1)
.FILTER_RANGE(3'b001), // wfm without PLL is broken
) uut (
.REFERENCECLK(CLK_25M),
.PLLOUTCORE(CLK_50M),
// .LOCK(P16),
.RESETB(1'b1),
.BYPASS(1'b0)
);
/* high-speed ADC */
assign ADC_CLK = HW_CLK;
assign ADC_CLK = CLK_50M;
reg [7:0] adc_buf = 8'b0;
reg [7:0] adc_ram [100];
reg [15:0] ram_pointer = 0;