mikelam 900c0e292f add PLL to generate 50MHz clock for ADC		2022-01-09 21:28:03 +08:00
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Inc	add PLL to generate 50MHz clock for ADC	2022-01-09 21:28:03 +08:00
Src	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00