mikelam 900c0e292f add PLL to generate 50MHz clock for ADC		2022-01-09 21:28:03 +08:00
.vscode	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00
Core	add PLL to generate 50MHz clock for ADC	2022-01-09 21:28:03 +08:00
Drivers	HSADC working (under 25MHz clock); FSMC working; make file can generate fpga bitstram as C array	2021-12-26 16:53:27 +08:00
FPGA	add PLL to generate 50MHz clock for ADC	2022-01-09 21:28:03 +08:00
.gitignore	add ethernet controller spi driver	2021-07-27 09:58:57 +08:00
.mxproject	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00
fpga.nix	change to STM32F103VFT6; add ADC and SW/LED IO labels; simple testing for 5V GND MOS switch	2021-08-31 17:38:28 +08:00
Makefile	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00
startup_stm32f103xg.s	change to STM32F103VFT6; add ADC and SW/LED IO labels; simple testing for 5V GND MOS switch	2021-08-31 17:38:28 +08:00
STM32F103VFTx_FLASH.ld	change to STM32F103VFT6; add ADC and SW/LED IO labels; simple testing for 5V GND MOS switch	2021-08-31 17:38:28 +08:00
Syrostan-C.jdebug	change to STM32F103VFT6; add ADC and SW/LED IO labels; simple testing for 5V GND MOS switch	2021-08-31 17:38:28 +08:00
Syrostan-C.jdebug.user	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00
Syrostan-MCU-C.ioc	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00