mikelam 900c0e292f add PLL to generate 50MHz clock for ADC		2022-01-09 21:28:03 +08:00
..
fsmc.pcf.bak	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00
fsmc.v.bak	use software FSMC to avoid FPGA strange inout issue	2022-01-09 20:30:28 +08:00
lvds.py	multiplexer working	2021-12-31 10:57:11 +08:00
makefile	HSADC working (under 25MHz clock); FSMC working; make file can generate fpga bitstram as C array	2021-12-26 16:53:27 +08:00
pinmap.pcf	add PLL to generate 50MHz clock for ADC	2022-01-09 21:28:03 +08:00
top.v	add PLL to generate 50MHz clock for ADC	2022-01-09 21:28:03 +08:00