Syrostan-MCU-C/FPGA/top.v

module top (
    input CLK_25M,
    input KEY,
    output LED,

    input FSMC_NL,
    input FSMC_NOE,
    input FSMC_NWE,
    input FSMC_NE1,
    input [15:0]FSMC_ADD,
    inout [7:0]FSMC_DAT,
    input [1:0]FSMC_NBL,
    output FSMC_CLK,
    output FSMC_NWAIT,

    output ADC_CLK,
    input [7:0]ADC_DAT,

    output DIO_OUT,
    output DIO_IO_SEL,
    output [2:0]DIO_CH_SEL,

    inout eem0_n_0,
    inout eem0_p_0,
    inout eem0_n_1,
    inout eem0_p_1,
    inout eem0_n_2,
    inout eem0_p_2,
    inout eem0_n_3,
    inout eem0_p_3,
    inout eem0_n_4,
    inout eem0_p_4,
    inout eem0_n_5,
    inout eem0_p_5,
    inout eem0_n_6,
    inout eem0_p_6,
    inout eem0_n_7,
    inout eem0_p_7,
    
    inout eem1_n_0,
    inout eem1_p_0,
    inout eem1_n_1,
    inout eem1_p_1,
    inout eem1_n_2,
    inout eem1_p_2,
    inout eem1_n_3,
    inout eem1_p_3,
    inout eem1_n_4,
    inout eem1_p_4,
    inout eem1_n_5,
    inout eem1_p_5,
    inout eem1_n_6,
    inout eem1_p_6,
    inout eem1_n_7,
    inout eem1_p_7,

    inout eem2_n_0,
    inout eem2_p_0,
    inout eem2_n_1,
    inout eem2_p_1,
    inout eem2_n_2,
    inout eem2_p_2,
    inout eem2_n_3,
    inout eem2_p_3,
    inout eem2_n_4,
    inout eem2_p_4,
    inout eem2_n_5,
    inout eem2_p_5,
    inout eem2_n_6,
    inout eem2_p_6,
    inout eem2_n_7,
    inout eem2_p_7,
);


/* LED */
    reg [31:0] counter = 32'b0;
    // assign LED = counter[24];
    // assign LED = ~KEY;

    always @ (posedge CLK_25M) begin
        counter <= counter + 1;
    end

/* high-speed ADC */
    wire CLK_80M;
    SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
                    .PLLOUT_SELECT("GENCLK"),
                    .DIVR(4'd4),
                    .DIVF(7'd15),
                    .DIVQ(3'd0),  //25MHz * (DIVF+1) / 2^DIVQ / (DIVR+1)

                    .FILTER_RANGE(3'b001),  // wfm without PLL is broken
                    ) uut (
                        .REFERENCECLK(CLK_25M),
                        .PLLOUTCORE(CLK_80M),
//                        .LOCK(P16),
                        .RESETB(1'b1),
                        .BYPASS(1'b0)
                    );

    parameter ADC_RAM_DEPTH = 16384;

    assign ADC_CLK = CLK_80M;
    reg [7:0] adc_buf = 8'b0;
    reg [7:0] adc_ram [0:ADC_RAM_DEPTH-1];
    reg [15:0] ram_pointer = 0;
    reg [7:0] adc_status = 8'h00;         //0:idle or sampling; 1: data available
    always @ (posedge ADC_CLK) begin
        if (adc_status[0]) begin
            adc_buf = ADC_DAT;
            adc_buf[7] = ~adc_buf[7];
            adc_ram[ram_pointer] = adc_buf;
            if (ram_pointer < ADC_RAM_DEPTH) begin
                adc_status[1] = 1'b0;
                ram_pointer++;
            end
            else begin
                // adc_status[0] = 1'b0;
                adc_status[1] = 1'b1;
                ram_pointer = 0;
            end
        end
    end

/* FSMC */
    reg [7:0] fsmc_buf;

    wire FSMC_RE = ~FSMC_NOE & ~FSMC_NE1;
    always @ (posedge FSMC_RE) begin   //read from FPGA
        // if (FSMC_ADD == 16'hffff)
        //     FSMC_DAT <= adc_status;
        // else
            FSMC_DAT <= adc_ram[FSMC_ADD];
    end

    wire FSMC_WE = ~FSMC_NWE & ~FSMC_NE1;
    always @ (posedge FSMC_WE) begin   //write to FPGA
        //4 bits for LVDS; 3 bits for channel select; 1 bit for IO direction control
        DIO_IO_SEL <= FSMC_ADD[0];
        DIO_CH_SEL <= FSMC_ADD[3:1];

        adc_status[0] = FSMC_ADD[4];
    end 

    // assign FSMC_DAT = FSMC_RE ? fsmc_buf : 8'hzz;
    // assign FSMC_CLK = adc_status[0];
    assign FSMC_NWAIT = adc_status[1];
    
/* LVDS */
    wire eem_ch0;
    wire eem_ch1;
    wire eem_ch2;
    wire eem_ch3;
    wire eem_ch4;
    wire eem_ch5;
    wire eem_ch6;
    wire eem_ch7;

    assign eem0_n_0 = eem_ch0;
    assign eem0_p_0 = ~eem_ch0;
    // assign eem0_n_1 = eem_ch1;
    // assign eem0_p_1 = ~eem_ch1;
    assign eem0_n_2 = eem_ch2;
    assign eem0_p_2 = ~eem_ch2;
    assign eem0_n_3 = eem_ch3;
    assign eem0_p_3 = ~eem_ch3;
    assign eem0_n_4 = eem_ch4;
    assign eem0_p_4 = ~eem_ch4;
    assign eem0_n_5 = eem_ch5;
    assign eem0_p_5 = ~eem_ch5;
    assign eem0_n_6 = eem_ch6;
    assign eem0_p_6 = ~eem_ch6;
    assign eem0_n_7 = eem_ch7;
    assign eem0_p_7 = ~eem_ch7;

    SB_IO #(
        .IO_STANDARD("SB_LVDS_INPUT"),  //"SB_LVCMOS" for output
        .PIN_TYPE(6'd1)
    ) SB_IO (
        .PACKAGE_PIN(eem0_n_1),
        .D_IN_0(eem_ch1)
    );

    assign eem_ch0 = counter[3];
    // assign eem_ch1 = counter[3];
    assign eem_ch2 = counter[3];
    assign eem_ch3 = counter[3];
    assign eem_ch4 = counter[3];
    assign eem_ch5 = counter[3];
    assign eem_ch6 = counter[3];
    assign eem_ch7 = counter[3];

    assign LED = eem_ch1;
    assign DIO_OUT = counter[24];

endmodule