197 lines
4.7 KiB
Verilog
197 lines
4.7 KiB
Verilog
module top (
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input CLK_25M,
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input KEY,
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output LED,
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input FSMC_NL,
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input FSMC_NOE,
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input FSMC_NWE,
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input FSMC_NE1,
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input [15:0]FSMC_ADD,
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inout [7:0]FSMC_DAT,
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input [1:0]FSMC_NBL,
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output FSMC_CLK,
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output FSMC_NWAIT,
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output ADC_CLK,
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input [7:0]ADC_DAT,
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output DIO_OUT,
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output DIO_IO_SEL,
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output [2:0]DIO_CH_SEL,
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inout eem0_n_0,
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inout eem0_p_0,
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inout eem0_n_1,
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inout eem0_p_1,
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inout eem0_n_2,
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inout eem0_p_2,
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inout eem0_n_3,
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inout eem0_p_3,
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inout eem0_n_4,
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inout eem0_p_4,
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inout eem0_n_5,
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inout eem0_p_5,
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inout eem0_n_6,
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inout eem0_p_6,
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inout eem0_n_7,
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inout eem0_p_7,
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inout eem1_n_0,
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inout eem1_p_0,
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inout eem1_n_1,
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inout eem1_p_1,
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inout eem1_n_2,
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inout eem1_p_2,
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inout eem1_n_3,
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inout eem1_p_3,
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inout eem1_n_4,
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inout eem1_p_4,
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inout eem1_n_5,
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inout eem1_p_5,
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inout eem1_n_6,
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inout eem1_p_6,
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inout eem1_n_7,
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inout eem1_p_7,
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inout eem2_n_0,
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inout eem2_p_0,
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inout eem2_n_1,
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inout eem2_p_1,
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inout eem2_n_2,
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inout eem2_p_2,
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inout eem2_n_3,
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inout eem2_p_3,
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inout eem2_n_4,
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inout eem2_p_4,
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inout eem2_n_5,
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inout eem2_p_5,
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inout eem2_n_6,
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inout eem2_p_6,
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inout eem2_n_7,
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inout eem2_p_7,
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);
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/* LED */
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reg [31:0] counter = 32'b0;
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// assign LED = counter[24];
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// assign LED = ~KEY;
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always @ (posedge CLK_25M) begin
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counter <= counter + 1;
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end
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/* high-speed ADC */
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wire CLK_80M;
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SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
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.PLLOUT_SELECT("GENCLK"),
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.DIVR(4'd4),
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.DIVF(7'd15),
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.DIVQ(3'd0), //25MHz * (DIVF+1) / 2^DIVQ / (DIVR+1)
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.FILTER_RANGE(3'b001), // wfm without PLL is broken
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) uut (
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.REFERENCECLK(CLK_25M),
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.PLLOUTCORE(CLK_80M),
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// .LOCK(P16),
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.RESETB(1'b1),
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.BYPASS(1'b0)
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);
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parameter ADC_RAM_DEPTH = 16384;
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assign ADC_CLK = CLK_80M;
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reg [7:0] adc_buf = 8'b0;
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reg [7:0] adc_ram [0:ADC_RAM_DEPTH-1];
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reg [15:0] ram_pointer = 0;
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reg [7:0] adc_status = 8'h00; //0:idle or sampling; 1: data available
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always @ (posedge ADC_CLK) begin
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if (adc_status[0]) begin
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adc_buf = ADC_DAT;
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adc_buf[7] = ~adc_buf[7];
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adc_ram[ram_pointer] = adc_buf;
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if (ram_pointer < ADC_RAM_DEPTH) begin
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adc_status[1] = 1'b0;
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ram_pointer++;
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end
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else begin
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// adc_status[0] = 1'b0;
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adc_status[1] = 1'b1;
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ram_pointer = 0;
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end
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end
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end
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/* FSMC */
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reg [7:0] fsmc_buf;
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wire FSMC_RE = ~FSMC_NOE & ~FSMC_NE1;
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always @ (posedge FSMC_RE) begin //read from FPGA
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// if (FSMC_ADD == 16'hffff)
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// FSMC_DAT <= adc_status;
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// else
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FSMC_DAT <= adc_ram[FSMC_ADD];
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end
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wire FSMC_WE = ~FSMC_NWE & ~FSMC_NE1;
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always @ (posedge FSMC_WE) begin //write to FPGA
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//4 bits for LVDS; 3 bits for channel select; 1 bit for IO direction control
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DIO_IO_SEL <= FSMC_ADD[0];
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DIO_CH_SEL <= FSMC_ADD[3:1];
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adc_status[0] = FSMC_ADD[4];
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end
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// assign FSMC_DAT = FSMC_RE ? fsmc_buf : 8'hzz;
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// assign FSMC_CLK = adc_status[0];
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assign FSMC_NWAIT = adc_status[1];
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/* LVDS */
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wire eem_ch0;
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wire eem_ch1;
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wire eem_ch2;
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wire eem_ch3;
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wire eem_ch4;
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wire eem_ch5;
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wire eem_ch6;
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wire eem_ch7;
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assign eem0_n_0 = eem_ch0;
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assign eem0_p_0 = ~eem_ch0;
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// assign eem0_n_1 = eem_ch1;
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// assign eem0_p_1 = ~eem_ch1;
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assign eem0_n_2 = eem_ch2;
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assign eem0_p_2 = ~eem_ch2;
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assign eem0_n_3 = eem_ch3;
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assign eem0_p_3 = ~eem_ch3;
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assign eem0_n_4 = eem_ch4;
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assign eem0_p_4 = ~eem_ch4;
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assign eem0_n_5 = eem_ch5;
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assign eem0_p_5 = ~eem_ch5;
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assign eem0_n_6 = eem_ch6;
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assign eem0_p_6 = ~eem_ch6;
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assign eem0_n_7 = eem_ch7;
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assign eem0_p_7 = ~eem_ch7;
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SB_IO #(
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.IO_STANDARD("SB_LVDS_INPUT"), //"SB_LVCMOS" for output
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.PIN_TYPE(6'd1)
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) SB_IO (
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.PACKAGE_PIN(eem0_n_1),
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.D_IN_0(eem_ch1)
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);
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assign eem_ch0 = counter[3];
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// assign eem_ch1 = counter[3];
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assign eem_ch2 = counter[3];
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assign eem_ch3 = counter[3];
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assign eem_ch4 = counter[3];
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assign eem_ch5 = counter[3];
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assign eem_ch6 = counter[3];
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assign eem_ch7 = counter[3];
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assign LED = eem_ch1;
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assign DIO_OUT = counter[24];
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endmodule |