• Joined on 2019-03-28
sb10q pushed to master at M-Labs/HeavyX 2019-04-17 16:08:39 +08:00
034ecc4d99 nmigen: run tests in verbose mode
4dd024942e nmigen: bump
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sb10q pushed to master at M-Labs/HeavyX 2019-04-09 00:48:28 +08:00
e3f47815e5 rust: add riscv32i
sb10q pushed to master at M-Labs/HeavyX 2019-04-09 00:10:01 +08:00
25fe837684 use upstream rust/llvm
sb10q pushed to master at M-Labs/HeavyX 2019-04-07 23:16:03 +08:00
c3992220e5 rustc: fix crates compilation
sb10q pushed to master at M-Labs/HeavyX 2019-04-07 00:45:05 +08:00
da982a60cc rustc: add libxml2 dep
sb10q pushed to master at M-Labs/HeavyX 2019-04-06 21:25:37 +08:00
0ef16ba90c llvm: use more up-to-date upstream, build for riscv
sb10q pushed to master at M-Labs/HeavyX 2019-04-06 20:06:10 +08:00
52dbb6275f rust: fix riscv target name
sb10q pushed to master at M-Labs/HeavyX 2019-04-06 19:16:43 +08:00
96b7248514 rustc: use more up-to-date upstream, build for riscv
sb10q pushed to master at M-Labs/HeavyX 2019-04-06 18:23:48 +08:00
b913a92a82 add rustc (WIP)
sb10q pushed to master at M-Labs/HeavyX 2019-04-06 15:21:03 +08:00
298514fe0a move fetch-llvm-clang.nix into llvm-hx.nix
sb10q pushed to master at M-Labs/HeavyX 2019-04-05 18:58:58 +08:00
1bf9b5eb2b add VexRiscv
sb10q pushed to master at M-Labs/HeavyX 2019-04-04 23:44:12 +08:00
584dba9ed0 add scala-spinalhdl
e56d2ad3c8 style
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sb10q pushed to master at M-Labs/HeavyX 2019-04-01 11:05:10 +08:00
466d85e719 reorganize
sb10q pushed to master at M-Labs/HeavyX 2019-04-01 10:49:49 +08:00
3dd10e6b9b add simple test for UART
472114c136 add binutils
ed53324019 add LLVM and Clang
7bac1cd3ef minor cleanup
e047e69f78 fix helloworld.nix