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18 Commits (0ea749954372cefbcfd286db46be464fcaff2385)

Author SHA1 Message Date
Ryan Summers 253a1f6f1d Adding format 2023-07-03 12:25:46 +02:00
Harry Ho fbcc3778d2 spi: Always delay for NSS setup time 
* Fixes the lack of setup time delay of an fixed-byte command that immediately follows an N-byte command.
* Extra 50ns will be inserted in-between fixed-byte commands but should be acceptable.
 2021-06-23 12:49:21 +08:00
Harry Ho 999ca5f08a spi: Replace delay_ns func pointer with delay on cortex-m 
* SPI NSS nanosecond delays now only takes place on Cortex-M CPUs
 2021-06-03 15:03:43 +08:00
Harry Ho ec20970a50 spi: Impose stricter NSS timing 2021-06-03 12:03:35 +08:00
Harry Ho 35b7924431 spi: Add back NSS high delay conditionally based on opcode type 2021-06-03 11:51:09 +08:00
Harry Ho d05d7f91e2 spi: Simplify all reg reads/writes as rw_n() 2021-06-03 11:51:09 +08:00
Harry Ho 27ba42c4fb spi: Introduce certain 1 & 3-byte opcodes to replace reg read/writes 2021-06-03 11:51:09 +08:00
Harry Ho 40a53cc0d6 spi: Fix Rx/Tx buffer logic & simplify 
* tx/rx: Rename wrap_addr to start_addr for clarity
* Fix RX logic, when advancing the tail pointer, not retrieving the stored RX buffer start address but the default value instead
* Fix TX logic, when advancing the head pointer for next transmission, not retrieving the stored TX buffer end address but the default value instead
* Rename SPI-related const's to match the datasheet: RERXDATA→RRXDATA, WEGPDATA→WGPDATA
* Remove useless const's for SRAM default addresses for TX buffer
* Simplify code
 2021-04-30 17:30:25 +08:00
Harry Ho b9b28f0725 Rename functions & classes for clarity 
* EthController → EthPhy
  * ::receive_next() → ::recv_packet()
  * ::send_raw_packet() → ::send_packet()
* SpiEth -> Enc424j600
  * ::read_from_mac() → ::read_mac_addr()
  * ::write_mac_address() → ::write_mac_addr()
* EthControllerError → Error
  * ::GeneralError → ::RegisterError
* spi::SpiPortError -> spi::Error
 2021-04-29 17:07:28 +08:00
occheung 1add94c12e Remove cortex-m dependencies for delay (#2) 
Co-Authored-By: occheung <dc@m-labs.hk>
Co-Committed-By: occheung <dc@m-labs.hk>
 2021-01-25 12:35:23 +08:00
occheung 26dabd4dc0 spi: add CS delay 2021-01-18 15:33:27 +08:00
Harry Ho 4ba5052623 Simplify, styling & spelling 2020-12-29 11:42:31 +08:00
Harry Ho ae0d77cbf1 Fix poor & unimplemented code 2020-12-28 17:06:31 +08:00
Harry Ho 7b313292ca Replace stm32f4xx_hal with embedded_hal in the library 2020-08-24 12:07:45 +08:00
Harry Ho 5b99525cd0 Reorganise spi consts 2020-08-17 15:51:25 +08:00
Harry Ho 82f4bef09f Add packet TX 2020-06-18 11:09:39 +08:00
Harry Ho 9b48a585cf Add packet RX 2020-06-17 17:04:18 +08:00
Harry Ho 4e4267e55a Add reading SFR registers via SPI 
* uses stm32f4xx_hal crate
 2020-06-15 16:18:34 +08:00