occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity
841 Commits 14 Branches 35 Tags 23 MiB
Commit Graph

120 Commits

Author SHA1 Message Date
Florent Kermarrec 2995f0a705 remove use of _r prefix on CSRs 2015-04-02 18:30:44 +08:00
Sebastien Bourdeauducq 88a1707ef9 soc: use new location of gpio module 2015-04-02 17:19:00 +08:00
Sebastien Bourdeauducq f124350555 runtime: disable kernel-CPU functions when kernel-CPU not present 2015-04-02 17:00:59 +08:00
Sebastien Bourdeauducq 4b66e3108a runtime: demonstrate basic inter-CPU communication 2015-04-02 16:54:08 +08:00
Sebastien Bourdeauducq 5fd7f68f48 targets/kc705: dual-CPU design 2015-04-02 16:53:57 +08:00
Yann Sionneau e9092edb98 Remove one RTIO out channel to free up some space for travis builds to succeed 2015-03-30 19:51:52 +08:00
Florent Kermarrec 494c670cd2 targets/artiq_ppro: use new sdram_controller_settings parameter 2015-03-21 23:19:16 +01:00
Robert Jördens fdca0a71ff add ARTIQMidiSoC based on pipistrello 2015-03-19 11:37:15 -06:00
Sebastien Bourdeauducq 7a1d60ee15 coredevice,runtime,language: add parameters to runtime exceptions, include information with RTIO errors 2015-03-13 14:55:18 +01:00
Sebastien Bourdeauducq 0416da8634 runtime/test: implement ttlout, clksel and dds functions 2015-03-12 13:14:06 +01:00
Sebastien Bourdeauducq 3122623c6f rtio: make 63-bit timestamp counter the default [soc] 2015-03-12 13:13:35 +01:00
Sebastien Bourdeauducq d38014b07d soc/runtime: import DDS/TTL tester (functions not accessible yet) 2015-03-11 22:02:19 +01:00
Sebastien Bourdeauducq 28bce9ee40 artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
Sebastien Bourdeauducq 15d09c0b94 runtime: use new uart tuning word function 2015-03-02 23:36:05 +00:00
Sebastien Bourdeauducq 4e5320be28 Merge branch 'master' of https://github.com/m-labs/artiq 2015-02-28 07:34:38 -07:00
Florent Kermarrec 9cf8db2f14 adapt code to MiSoC's changes 2015-02-28 07:34:11 -07:00
Sébastien Bourdeauducq 7028d85255 targets/ppro: disable L2 2015-02-27 18:02:21 -07:00
Joe Britton 0127de9bb5 soc: add_cpu_csr_region -> add_csr_region 2015-02-27 15:02:28 -07:00
Sebastien Bourdeauducq 61f33a9a04 soc/ad9858: do not put code in __init__.py 2015-02-26 23:31:43 -07:00
Sebastien Bourdeauducq da917f768e initial kc705 support 2015-02-26 21:50:52 -07:00
Sebastien Bourdeauducq f7232fd3d1 support exceptions raised by RPCs 2014-12-20 21:33:22 +08:00
Sebastien Bourdeauducq 0d10ae7580 rpc: support all data types as parameters 2014-12-19 12:46:24 +08:00
Sebastien Bourdeauducq 059608d1fd dds: fix phase modes 2014-12-09 13:50:33 +08:00
Sebastien Bourdeauducq fc690ead75 runtime: support clock switching 2014-12-02 14:06:32 +08:00
Sebastien Bourdeauducq 94218f785e comm_serial: cleanup 2014-12-02 11:09:02 +08:00
Yann Sionneau 20adb57140 comm_serial: allow to use dynamic baudrate 2014-12-02 10:42:14 +08:00
Sebastien Bourdeauducq c591f1a74d targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG 2014-12-01 18:53:29 +08:00
Sebastien Bourdeauducq cd587e4f12 rtio: do housekeeping in gateware 2014-12-01 17:32:36 +08:00
Sebastien Bourdeauducq 99d530e498 targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA 2014-12-01 17:31:35 +08:00
Sebastien Bourdeauducq 50e0bf3280 rtio: optimize flag handling 2014-12-01 14:29:50 +08:00
Sebastien Bourdeauducq 572eecc57b rtio: stricter upper bound on guard time to avoid race condition 2014-12-01 14:27:03 +08:00
Sebastien Bourdeauducq 7166ca82d1 targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%) 2014-11-30 22:31:55 +08:00
Sebastien Bourdeauducq 1f6441948d more TTL channels and larger input FIFOs on Papilio Pro 2014-11-30 15:50:57 +08:00
Sebastien Bourdeauducq e5286c57ab rtio: fix input FIFO depth config 2014-11-30 12:12:35 +08:00
Sebastien Bourdeauducq bf745e53c9 rtio: register FIFO output to improve timing 2014-11-30 10:51:12 +08:00
Sebastien Bourdeauducq dda4002ae1 rtio/phy: fix input synchronization 2014-11-30 10:50:48 +08:00
Sebastien Bourdeauducq c78c5a2b4f rtio: fix guard cycle computation 2014-11-30 01:00:52 +08:00
Sebastien Bourdeauducq 39c4b5416f targets/ARTIQMiniSoC: 125MHz RTIO clocking 2014-11-30 01:00:27 +08:00
Sebastien Bourdeauducq 9aafe89518 rtio: use Record 2014-11-30 00:59:39 +08:00
Sebastien Bourdeauducq 901073acf3 asynchronous RTIO 2014-11-30 00:13:54 +08:00
Sebastien Bourdeauducq 44ec3eae3d soc/target: use minicon by default 2014-11-28 10:21:43 +08:00
Sebastien Bourdeauducq 65567e1201 soc/target: remap RTIO to avoid conflict with Ethernet MAC+PHY 2014-11-21 15:51:51 -08:00
Sebastien Bourdeauducq dfd779c7c5 core: add underflow recovery function 2014-11-20 12:38:52 -08:00
Sebastien Bourdeauducq 1780759327 dds: phase control (mostly untested) 2014-11-20 12:32:56 -08:00
Sebastien Bourdeauducq 17f5a31320 runtime/dds: fix reset glitches 2014-11-15 11:23:23 -07:00
Sebastien Bourdeauducq 5105b88302 rtio: raise input overflow exception 2014-10-21 23:41:02 +08:00
Sebastien Bourdeauducq 9a14081031 rtio: add pileup count reporting 2014-10-21 23:14:01 +08:00
Sebastien Bourdeauducq 346cca9e90 soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC 2014-10-21 18:40:08 +08:00
Sebastien Bourdeauducq 61a50ee53c reorganize for devices/controllers 2014-10-19 23:51:49 +08:00
Sebastien Bourdeauducq 0c9632d71b runtime/exception_raise: never return 2014-10-15 16:11:28 +08:00