occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)

This commit is contained in:
Sebastien Bourdeauducq 2014-11-30 22:31:55 +08:00
parent 1f6441948d
commit 7166ca82d1
1 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
soc/targets/artiq.py
View File

@ -1,4 +1,5 @@
from migen.fhdl.std import *
from migen.bank import wbgen
from mibuild.generic_platform import *
from misoclib import gpio
@ -70,7 +71,7 @@ TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 13
"rtio": None # mapped on Wishbone instead
}
csr_map.update(BaseSoC.csr_map)
@ -101,6 +102,11 @@ class ARTIQMiniSoC(BaseSoC):
clk_freq=125000000,
ififo_depth=512)
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
if with_test_gen:
self.submodules.test_gen = _TestGen(platform.request("ttl", 8))