forked from M-Labs/artiq
targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)
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@ -1,4 +1,5 @@
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from migen.fhdl.std import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib import gpio
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@ -70,7 +71,7 @@ TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
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class ARTIQMiniSoC(BaseSoC):
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csr_map = {
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"rtio": 13
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"rtio": None # mapped on Wishbone instead
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}
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csr_map.update(BaseSoC.csr_map)
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@ -101,6 +102,11 @@ class ARTIQMiniSoC(BaseSoC):
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clk_freq=125000000,
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ififo_depth=512)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
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self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
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if with_test_gen:
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self.submodules.test_gen = _TestGen(platform.request("ttl", 8))
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