rtio: make 63-bit timestamp counter the default [soc]

artiq/gateware/rtio/core.py

@@ -294,7 +294,7 @@ class _RTIOBankI(Module):
 
 
 class RTIO(Module, AutoCSR):
-    def __init__(self, phy, clk_freq, counter_width=32,
+    def __init__(self, phy, clk_freq, counter_width=63,
                  ofifo_depth=64, ififo_depth=64,
                  guard_io_cycles=20):
         fine_ts_width = get_fine_ts_width(phy.rbus)

soc/targets/artiq_ppro.py

@@ -119,6 +119,7 @@ class ARTIQMiniSoC(BaseSoC):
             output_only_pads=set(rtio_outs))
         self.submodules.rtio = rtio.RTIO(self.rtiophy,
                                          clk_freq=125000000,
+                                         counter_width=32,
                                          ififo_depth=512)
 
         rtio_csrs = self.rtio.get_csrs()