df71b82037
coredevice/i2c: fix imports
2016-03-05 00:43:13 +08:00
a8a74d7840
targets/kc705: enable I2C for all hardware adapters
2016-03-05 00:19:59 +08:00
6b8efd10fd
runtime/i2c: fix artiq_raise_from_c invokation
2016-03-05 00:19:08 +08:00
2f1a2782d2
coredevice: add I2C, PCA9548, TCA6424A drivers
2016-03-05 00:17:41 +08:00
790269eee7
master/worker_db: make arguments optional in DDB entries
2016-03-05 00:17:08 +08:00
ff4a46c278
runtime/i2c: make syscalls more ARTIQ-Python-friendly
2016-03-05 00:16:23 +08:00
3364827744
ttl/TTLClockGen: fix FTW computation with ref_multiplier != 1
2016-03-04 16:59:59 +08:00
4352d15016
coredevice/core: add ref_multiplier and coarse_ref_period attributes
2016-03-04 16:59:35 +08:00
354a62f5d0
Merge branch 'master' of github.com:m-labs/artiq
2016-03-04 16:51:48 +08:00
whitequark
6e44c5424d
coredevice.ttl: add missed int64 conversion.
2016-03-04 08:37:43 +00:00
7ff0c89d51
kc705.clock: add all spi buses
2016-03-04 00:03:48 +01:00
669fbaa4f1
ad53xx->ad5360 and refactor
2016-03-04 00:00:25 +01:00
dc6d116824
spi: have write() delay by transfer duration
2016-03-03 21:57:27 +01:00
c2fcefc31f
runtime/rtio: cleanup include
2016-03-03 19:48:06 +08:00
423ca03f3b
runtime: bit-banged i2c support (untested)
2016-03-03 17:46:42 +08:00
whitequark
73bfbe51db
compiler: reject lambdas used as kernel functions ( fixes #313 ).
2016-03-03 08:33:28 +00:00
cfe72c72a2
gateware/kc705: add I2C GPIO core for QC2
2016-03-03 15:32:10 +08:00
a901971e58
gateware/soc: factor code to connect CSR device to kernel CPU
2016-03-03 15:12:15 +08:00
b662a6fcbd
gateware/nist_{clock,qc2}: do not conflict with KC705 I2C
2016-03-03 15:10:50 +08:00
9af12230c8
soc: add timer to kernel CPU system
2016-03-03 13:19:17 +08:00
b83b113f3c
gui/moninj: make widgets look less like buttons
2016-03-03 10:48:17 +08:00
0c97043a20
gateware/nist_clock: pin assignment corrections from David Leibrandt
2016-03-03 10:03:49 +08:00
d3f36ce784
kc705: add false paths for ethernet phy
...
* vivado prefers rsys_clk over sys_clk (despite the assignment hierarchy)
(We need DONT_TOUCH and/or KEEP verilog annotations to fix this)
2016-03-02 19:56:24 +01:00
9969cd85de
ad53xx: ldac may be none
2016-03-02 15:50:02 +01:00
f5dee455f5
test/worker: test exception logging
2016-03-02 17:12:22 +08:00
763a4d3011
rpctool: use pprint in interactive mode
2016-03-02 11:47:34 +08:00
d0d50d74eb
rpctool: interactive mode
2016-03-02 11:45:51 +08:00
946bd84b58
protocols/pc_rpc: support retrieving selected target
2016-03-02 11:45:31 +08:00
1e4bccae20
ad53xx: add
2016-03-02 00:12:01 +01:00
162ecdd574
spi: cleanup, add frequency_to_div()
2016-03-02 00:11:17 +01:00
d973eb879f
coredevice.spi: docstring fix
2016-03-01 22:42:00 +01:00
f754d2c117
Merge branch 'spimaster'
...
* spimaster: (52 commits)
runtime/rtio: rtio_process_exceptional_status() has only one user
coredevice.spi, doc/manual: add spi
kc705: move ttl channels together again, update doc
runtime: rt2wb_input -> rtio_input_data
examples/tdr: adapt to compiler changes
bridge: really fix O/OE
runtime: define constants for ttl addresses
coredevice.ttl: fix sensitivity
bridge: fix ttl o/oe addresses
runtime: refactor ttl*()
rtio: rm rtio_write_and_process_status
coredevice.spi: unused import
rt2wb, exceptions: remove RTIOTimeout
gateware.spi: delay only writes to data register, update doc
nist_clock: disable spi1/2
runtime/rt2wb: use input/output terminology and add (async) input
examples: update device_db for nist_clock spi
gateware.spi: rework wb bus sequence
nist_clock: rename spi*.ce to spi*.cs_n
nist_clock: add SPIMasters to spi buses
...
2016-03-01 22:08:08 +01:00
5ba753425d
runtime/rtio: rtio_process_exceptional_status() has only one user
2016-03-01 21:38:51 +01:00
0456169558
coredevice.spi, doc/manual: add spi
2016-03-01 21:29:09 +01:00
2cc1dfaee3
kc705: move ttl channels together again, update doc
2016-03-01 19:40:32 +01:00
f30dc4b39e
runtime: rt2wb_input -> rtio_input_data
2016-03-01 19:22:42 +01:00
baf7b0dcf2
examples/tdr: adapt to compiler changes
2016-03-01 19:04:03 +01:00
81b35be574
bridge: really fix O/OE
2016-03-01 18:49:04 +01:00
135643e3a6
runtime: define constants for ttl addresses
2016-03-01 18:22:42 +01:00
3aebbbdb61
coredevice.ttl: fix sensitivity
2016-03-01 18:22:03 +01:00
6f9656dcbe
bridge: fix ttl o/oe addresses
2016-03-01 18:19:06 +01:00
8adef12781
runtime: refactor ttl*()
...
* remove rt2wb_output
* remove ttl_*() ttl.c ttl.h
* use rtio_output() and rtio_input_timestamp()
* adapt coredevice/compiler layer
* adapt bridge to not artiq_raise_from_c()
2016-03-01 16:36:59 +01:00
aa10791ddf
rtio: rm rtio_write_and_process_status
2016-03-01 15:40:35 +01:00
29776fae3f
coredevice.spi: unused import
2016-03-01 15:38:40 +01:00
324660ab40
rt2wb, exceptions: remove RTIOTimeout
...
Assume that rt2wb transactions either collide and are then
reported (https://github.com/m-labs/artiq/issues/308 ) or that
they complete and the delay with which they complete does not matter.
If a transaction is ack'ed with a delay because the WB core's downstream
logic is busy, that may lead to a later collision with another WB
transaction.
2016-03-01 14:44:07 +01:00
c2fe9a08ae
gateware.spi: delay only writes to data register, update doc
2016-03-01 14:14:38 +01:00
whitequark
7e16da4a77
transforms.llvm_ir_generator: ignore assignments of None ( fixes #309 ).
2016-03-01 12:26:42 +00:00
c7d48a1765
coredevice/TTLOut: add dummy output function
2016-03-01 19:03:10 +08:00
18efca0f0a
Merge branch 'master' of github.com:m-labs/artiq
2016-03-01 14:49:16 +08:00
b0526c3354
protocols/pipe_ipc: fix resource leak on Windows
2016-03-01 14:49:04 +08:00
