forked from M-Labs/artiq
Merge branch 'master' of github.com:m-labs/artiq
This commit is contained in:
commit
18efca0f0a
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@ -477,7 +477,7 @@ class ASTTypedRewriter(algorithm.Transformer):
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target=node.target, iter=node.iter, body=node.body, orelse=node.orelse,
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trip_count=None, trip_interval=None,
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keyword_loc=node.keyword_loc, in_loc=node.in_loc, for_colon_loc=node.for_colon_loc,
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else_loc=node.else_loc, else_colon_loc=node.else_colon_loc)
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else_loc=node.else_loc, else_colon_loc=node.else_colon_loc, loc=node.loc)
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return node
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def visit_withitem(self, node):
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@ -6,7 +6,6 @@ import os
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import subprocess
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import tempfile
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import artiq
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from artiq import __artiq_dir__ as artiq_dir
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from artiq.frontend.bit2bin import bit2bin
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@ -18,13 +17,13 @@ def get_argparser():
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epilog="""\
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Valid actions:
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* proxy: load the flash proxy bitstream
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* bitstream: write bitstream to flash
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* proxy: load the flash proxy gateware bitstream
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* gateware: write gateware bitstream to flash
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* bios: write bios to flash
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* runtime: write runtime to flash
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* storage: write storage image to flash
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* load: load bitstream into device (volatile but fast)
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* start: trigger the target to (re)load its bitstream from flash
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* load: load gateware bitstream into device (volatile but fast)
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* start: trigger the target to (re)load its gateware bitstream from flash
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Prerequisites:
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@ -42,7 +41,7 @@ Prerequisites:
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parser.add_argument("-f", "--storage", help="write file to storage area")
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parser.add_argument("-d", "--dir", help="look for files in this directory")
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parser.add_argument("ACTION", nargs="*",
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default="proxy bitstream bios runtime start".split(),
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default="proxy gateware bios runtime start".split(),
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help="actions to perform, default: %(default)s")
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return parser
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@ -55,7 +54,7 @@ def main():
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"kc705": {
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"chip": "xc7k325t",
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"start": "xc7_program xc7.tap",
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"bitstream": 0x000000,
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"gateware": 0x000000,
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"bios": 0xaf0000,
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"runtime": 0xb00000,
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"storage": 0xb80000,
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@ -63,7 +62,7 @@ def main():
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"pipistrello": {
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"chip": "xc6slx45",
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"start": "xc6s_program xc6s.tap",
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"bitstream": 0x000000,
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"gateware": 0x000000,
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"bios": 0x170000,
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"runtime": 0x180000,
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"storage": 0x200000,
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@ -83,23 +82,23 @@ def main():
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proxy_base = "bscan_spi_{}.bit".format(config["chip"])
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proxy = None
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for p in [opts.dir, os.path.expanduser("~/.migen"),
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"/usr/local/share/migen", "/usr/share/migen"]:
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"/usr/local/share/migen", "/usr/share/migen"]:
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proxy_ = os.path.join(p, proxy_base)
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if os.access(proxy_, os.R_OK):
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proxy = "jtagspi_init 0 {}".format(proxy_)
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break
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if not proxy:
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raise SystemExit(
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"proxy bitstream {} not found".format(proxy_base))
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"proxy gateware bitstream {} not found".format(proxy_base))
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prog.append(proxy)
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elif action == "bitstream":
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elif action == "gateware":
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bin = os.path.join(opts.dir, "top.bin")
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if not os.access(bin, os.R_OK):
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bin = tempfile.mkstemp()[1]
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bit = os.path.join(opts.dir, "top.bit")
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conv = True
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prog.append("jtagspi_program {} 0x{:x}".format(
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bin, config["bitstream"]))
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bin, config["gateware"]))
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elif action == "bios":
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prog.append("jtagspi_program {} 0x{:x}".format(
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os.path.join(opts.dir, "bios.bin"), config["bios"]))
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@ -93,11 +93,11 @@ Preparing the core device FPGA board
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You now need to flash 3 things on the FPGA board:
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1. The FPGA bitstream
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1. The FPGA gateware bitstream
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2. The BIOS
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3. The ARTIQ runtime
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They are all shipped in our Conda packages, along with the required flash proxy bitstreams.
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They are all shipped in our Conda packages, along with the required flash proxy gateware bitstreams.
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First you need to install OpenOCD. Then, you can flash the board:
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@ -169,11 +169,11 @@ and the ARTIQ kernels.
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Preparing the core device FPGA board
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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These steps are required to generate bitstream (``.bit``) files, build the MiSoC BIOS and ARTIQ runtime, and flash FPGA boards. If the board is already flashed, you may skip those steps and go directly to `Installing the host-side software`.
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These steps are required to generate gateware bitstream (``.bit``) files, build the MiSoC BIOS and ARTIQ runtime, and flash FPGA boards. If the board is already flashed, you may skip those steps and go directly to `Installing the host-side software`.
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* Install the FPGA vendor tools (e.g. Xilinx ISE and/or Vivado):
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* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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* Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build gateware bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
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* The Pipistrello is supported by Webpack, the KC705 is not.
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@ -208,9 +208,9 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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.. _install-flash-proxy:
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* Install the required flash proxy bitstreams:
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* Install the required flash proxy gateware bitstreams:
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The purpose of the flash proxy bitstream is to give programming software fast JTAG access to the flash connected to the FPGA.
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The purpose of the flash proxy gateware bitstream is to give programming software fast JTAG access to the flash connected to the FPGA.
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* Pipistrello and KC705:
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@ -243,7 +243,7 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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:ref:`installing the host-side software <installing-the-host-side-software>`.
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* Build the bitstream, BIOS and runtime by running:
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* Build the gateware bitstream, BIOS and runtime by running:
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::
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$ cd ~/artiq-dev
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@ -270,7 +270,7 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
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.. note:: The `-t` option specifies the board your are targeting. Available options are ``kc705`` and ``pipistrello``.
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* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the bitstream that was newly written into the flash): ::
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* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
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$ make -C ~/artiq-dev/misoc/tools # do only once
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$ ~/artiq-dev/misoc/tools/flterm --port /dev/ttyUSB1
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