forked from M-Labs/artiq
Robert Jördens
f754d2c117
* spimaster: (52 commits) runtime/rtio: rtio_process_exceptional_status() has only one user coredevice.spi, doc/manual: add spi kc705: move ttl channels together again, update doc runtime: rt2wb_input -> rtio_input_data examples/tdr: adapt to compiler changes bridge: really fix O/OE runtime: define constants for ttl addresses coredevice.ttl: fix sensitivity bridge: fix ttl o/oe addresses runtime: refactor ttl*() rtio: rm rtio_write_and_process_status coredevice.spi: unused import rt2wb, exceptions: remove RTIOTimeout gateware.spi: delay only writes to data register, update doc nist_clock: disable spi1/2 runtime/rt2wb: use input/output terminology and add (async) input examples: update device_db for nist_clock spi gateware.spi: rework wb bus sequence nist_clock: rename spi*.ce to spi*.cs_n nist_clock: add SPIMasters to spi buses ... |
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CONTRIBUTING.rst | ||
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RELEASING.rst | ||
setup.cfg | ||
setup.py | ||
versioneer.py |
README.rst
.. image:: doc/logo/artiq.png ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) is a next-generation control system for quantum information experiments. It is developed in partnership with the Ion Storage Group at NIST, and its applicability reaches beyond ion trapping. The system features a high-level programming language that helps describing complex experiments, which is compiled and executed on dedicated hardware with nanosecond timing resolution and sub-microsecond latency. Technologies employed include Python, Migen, MiSoC/mor1kx, LLVM and llvmlite. Website: https://m-labs.hk/artiq Copyright (C) 2014-2016 M-Labs Limited. Licensed under GNU GPL version 3.