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7,491 Commits 14 Branches 35 Tags 23 MiB
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7491 Commits

Author SHA1 Message Date
Robert Jördens b619f657b9 phaser: doc tweaks 2020-09-12 19:59:49 +02:00
Robert Jördens c3728678d6 phaser: document, elaborate comments, some fixes 2020-09-12 17:35:14 +00:00
Robert Jördens e505dfed5b phaser: refactor coredevice driver 2020-09-12 14:17:40 +00:00
Robert Jördens fdd2d6f2fb phaser: SI methods 2020-09-12 11:02:37 +00:00
Sebastien Bourdeauducq bff611a888 test: relax test_dma_playback_time on Zynq 2020-09-11 11:21:45 +08:00
Robert Jördens 4e24700205 phaser: spelling 2020-09-09 16:52:52 +00:00
Robert Jördens 8aaeaa604e phaser: share_lut 2020-09-07 16:06:35 +00:00
Robert Jördens e69bb0aeb3 phaser: add comment about get_dac_data 2020-09-07 16:06:16 +00:00
pca006132 6195b1d3a0 rpc: fixed _write_bool 
Closes #1519
 2020-09-04 13:49:22 +08:00
Robert Jördens 56aa22caeb fastino: document/cleanup 
* added documentation on `update`/`hold` mechanism
* mask machine unit values
* cleanup coredevice driver

close #1518
 2020-09-03 17:44:26 +02:00
Astro 1b475bdac4 build_soc: remove assertion that was used for test runs 2020-09-03 20:24:18 +08:00
Harry Ho 458a411320
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516) 2020-09-03 15:08:31 +08:00
Sebastien Bourdeauducq 47e88dfcbe Revert "test: temporarily disable test_async_throughput" 
This reverts commit f0289d49ab.
 2020-09-03 14:19:55 +08:00
Astro 002a71dd8d build_soc: rename identifier_str to gateware_identifier_str 2020-09-02 00:00:57 +08:00
Sebastien Bourdeauducq 4398a2d5fa test: relax loopback gate timing 2020-09-01 17:50:09 +08:00
Sebastien Bourdeauducq f0289d49ab test: temporarily disable test_async_throughput 
M-Labs/artiq-zynq#104
 2020-09-01 17:49:40 +08:00
Sebastien Bourdeauducq 8d5dc0ad2a test: relax test_pulse_rate on Zynq 2020-09-01 17:08:26 +08:00
Sebastien Bourdeauducq f294d039b3 test: skip NonexistentI2CBus if I2C is not supported 2020-09-01 16:47:04 +08:00
Astro 91df3d7290 build_soc: override identifier_str only for gateware 2020-09-01 10:46:39 +08:00
Harry Ho 3d84135810 examples: add Metlino master, Sayma satellite with TTLOuts via FMC 2020-08-31 16:21:45 +08:00
Harry Ho dfbf3311cb sayma_amc: add support for 4x DIO output channels via FMC 2020-08-31 16:21:45 +08:00
Harry Ho 1ad9deaf91 fmcdio_vhdci_eem: fix pin naming 2020-08-31 16:21:45 +08:00
Astro 45ae6202c0 build_soc: add identifier_str override option 
Signed-off-by: Stephan Maka <stephan@spaceboyz.net>
 2020-08-31 11:48:58 +08:00
Robert Jördens 272dc5d36a phaser: documentation 2020-08-28 16:36:44 +00:00
pca006132 b2572003ac RPC: optimization by caching 
This reduced the calls needed for socket send/recv.
 2020-08-28 14:58:34 +08:00
pca006132 69f0699ebd test: improved test_performance 
1. Added tests for small payload.
2. Added statistics.
 2020-08-28 14:58:34 +08:00
Sebastien Bourdeauducq 7cf974a6a7 comm_kernel: fix typo 2020-08-28 12:25:23 +08:00
Robert Jördens 68bfa04abb phaser: trf readback strobe spi changes 2020-08-27 15:31:42 +00:00
Robert Jördens 96fc248d7c phaser: synchronize multidds to frame 2020-08-27 14:28:19 +00:00
Robert Jördens c10ac2c92a phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb) 2020-08-27 14:26:09 +00:00
Robert Jördens e5e2392240 phaser: wire up multidds 2020-08-26 17:12:41 +00:00
Robert Jördens d1be1212ab phaser: coredevice shim, dds [wip] 2020-08-26 15:10:50 +00:00
pca006132 26bc5d2405 Updated release notes 2020-08-26 14:17:06 +08:00
pca006132 aac2194759 Ported rpc changes to or1k 2020-08-26 14:17:06 +08:00
pca006132 7181ff66a6 compiler: improved rpc performance for list and array 
1. Removed duplicated tags before each elements.
2. Use numpy functions to speedup parsing.
 2020-08-26 14:17:06 +08:00
pca006132 cfddc13294 test: fixed test_performance 
Added more tests and use normal rpc instead of async rpc.

Async RPC does not represent the real throughput which is limited by the
hardware and the network. Normal RPC which requires a response from the
remote is closer to real usecases.
 2020-08-26 14:17:06 +08:00
Robert Jördens 20fcfd95e9 phaser: coredevice shim, readback fix 2020-08-24 15:46:31 +00:00
Robert Jördens bcefb06e19 phaser: ddb template, split crc 2020-08-24 14:51:50 +00:00
Robert Jördens 11c9def589 phaser: readback delay, test fastlink 2020-08-24 14:49:36 +00:00
Paweł Kulik eb350c3459 Drive SFP0 TX_DISABLE low during startup (as was in Kasli v1.1). Fixes Ethernet on SFP modules with pullup on this line. 
Signed-off-by: Paweł Kulik <pawel.kulik@creotech.pl>
 2020-08-24 21:39:53 +08:00
Robert Jördens 63e4b95325 fastlink: rework crc injection 2020-08-23 19:41:13 +00:00
Robert Jördens a27a03ab3c fastlink: fix crc vs data width 2020-08-23 19:02:50 +00:00
Robert Jördens 7e584d0da1 fastino: use fastlink 2020-08-22 11:56:23 +00:00
Robert Jördens 3e99f1ce5a phaser: refactor link 2020-08-22 11:56:23 +00:00
Robert Jördens a34a647ec4 phaser: refactor fastlink 2020-08-22 11:56:23 +00:00
Robert Jördens aa0154d8e2 phaser: initial 2020-08-22 11:56:23 +00:00
Sebastien Bourdeauducq 5f6aa02b61 gui: unbreak background 2020-08-14 13:14:45 +08:00
David Nadlinger 69718fca90 gui: Improve fuzzy-select heuristics 
Even though the code already used non-greedy wildcards before,
it would not find the shortest match, as earlier match starts
would still take precedence.

This could possibly be sped up a bit in CPython by doing
everything inside re using lookahead-assertion trickery, but the
current code is already imperceptibly fast for hundreds of
choices.
 2020-08-14 02:13:45 +01:00
pca006132 a46573e97a Revert "test: set uart log level to INFO for DMA tests" 
This reverts commit b05cbcbc24.
 2020-08-13 12:44:33 +08:00
pca006132 b05cbcbc24 test: set uart log level to INFO for DMA tests 2020-08-13 12:24:57 +08:00