forked from M-Labs/artiq
phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb)
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@ -42,6 +42,13 @@ PHASER_SEL_TRF1 = 1 << 2
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PHASER_SEL_ATT0 = 1 << 3
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PHASER_SEL_ATT1 = 1 << 4
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PHASER_STA_DAC_ALARM = 1 << 0
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PHASER_STA_TRF0_LD = 1 << 1
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PHASER_STA_TRF1_LD = 1 << 2
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PHASER_STA_TERM0 = 1 << 3
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PHASER_STA_TERM1 = 1 << 4
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PHASER_STA_SPI_IDLE = 1 << 5
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class Phaser:
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kernel_invariants = {"core", "channel_base", "t_frame"}
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@ -57,23 +64,23 @@ class Phaser:
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@kernel
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def init(self):
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board_id = self.read(PHASER_ADDR_BOARD_ID)
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board_id = self.read8(PHASER_ADDR_BOARD_ID)
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if board_id != PHASER_BOARD_ID:
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raise ValueError("invalid board id")
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delay(20*us)
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@kernel
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def write(self, addr, data):
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def write8(self, addr, data):
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"""Write data to a Phaser FPGA register.
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:param addr: Address to write to.
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:param data: Data to write.
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"""
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rtio_output((self.channel_base << 8) | addr | 0x80, data)
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rtio_output((self.channel_base << 8) | (addr & 0x7f) | 0x80, data)
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delay_mu(int64(self.t_frame))
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@kernel
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def read(self, addr):
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def read8(self, addr) -> TInt32:
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"""Read from Phaser FPGA register.
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TODO: untested
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@ -81,40 +88,65 @@ class Phaser:
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:param addr: Address to read from.
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:return: The data read.
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"""
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rtio_output((self.channel_base << 8) | addr, 0)
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rtio_output((self.channel_base << 8) | (addr & 0x7f), 0)
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response = rtio_input_data(self.channel_base)
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return response >> self.miso_delay
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@kernel
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def write32(self, addr, data: TInt32):
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for offset in range(4):
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byte = data >> 24
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self.write8(addr + offset, byte)
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data <<= 8
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@kernel
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def read32(self, addr) -> TInt32:
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data = 0
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for offset in range(4):
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data <<= 8
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data |= self.read8(addr + offset)
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delay(20*us) # slack
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return data
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@kernel
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def write16(self, addr, data: TInt32):
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self.write8(addr, data >> 8)
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self.write8(addr + 1, data)
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@kernel
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def read16(self, addr) -> TInt32:
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return (self.read8(addr) << 8) | self.read8(addr)
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@kernel
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def set_leds(self, leds):
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self.write(PHASER_ADDR_LED, leds)
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self.write8(PHASER_ADDR_LED, leds)
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@kernel
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def set_fan(self, duty):
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self.write(PHASER_ADDR_FAN, duty)
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self.write8(PHASER_ADDR_FAN, duty)
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@kernel
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def set_cfg(self, clk_sel=0, dac_resetb=1, dac_sleep=0, dac_txena=1,
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trf0_ps=0, trf1_ps=0, att0_rstn=1, att1_rstn=1):
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self.write(PHASER_ADDR_CFG,
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self.write8(PHASER_ADDR_CFG,
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(clk_sel << 0) | (dac_resetb << 1) | (dac_sleep << 2) |
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(dac_txena << 3) | (trf0_ps << 4) | (trf1_ps << 5) |
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(att0_rstn << 6) | (att1_rstn << 7))
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@kernel
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def get_sta(self):
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return self.read(PHASER_ADDR_STA)
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return self.read8(PHASER_ADDR_STA)
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@kernel
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def get_crc_err(self):
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return self.read(PHASER_ADDR_CRC_ERR)
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return self.read8(PHASER_ADDR_CRC_ERR)
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@kernel
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def get_dac_data(self, ch) -> TInt32:
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data = 0
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for addr in range(4):
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data <<= 8
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data |= self.read(PHASER_ADDR_DAC0_DATA + (ch << 4) + addr)
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data |= self.read8(PHASER_ADDR_DAC0_DATA + (ch << 4) + addr)
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delay(20*us) # slack
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return data
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@ -122,32 +154,43 @@ class Phaser:
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def set_dac_test(self, ch, data: TInt32):
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for addr in range(4):
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byte = (data >> 24) & 0xff
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self.write(PHASER_ADDR_DAC0_TEST + (ch << 4) + addr, byte)
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self.write8(PHASER_ADDR_DAC0_TEST + (ch << 4) + addr, byte)
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data <<= 8
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return data
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@kernel
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def set_duc_cfg(self, ch, clr=0, clr_once=0, select=0):
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self.write(PHASER_ADDR_DUC0_CFG + (ch << 4),
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self.write8(PHASER_ADDR_DUC0_CFG + (ch << 4),
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(clr << 0) | (clr_once << 1) | (select << 2))
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@kernel
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def set_duc_frequency_mu(self, ch, ftw):
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self.write32(PHASER_ADDR_DUC0_F + (ch << 4), ftw)
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@kernel
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def set_duc_phase_mu(self, ch, pow):
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self.write16(PHASER_ADDR_DUC0_P + (ch << 4), pow)
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@kernel
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def duc_stb(self):
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self.write8(PHASER_ADDR_DUC_STB, 0)
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@kernel
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def spi_cfg(self, select, div, end, clk_phase=0, clk_polarity=0,
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half_duplex=0, lsb_first=0, offline=0):
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self.write(PHASER_ADDR_SPI_SEL, select)
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self.write(PHASER_ADDR_SPI_DIV, div)
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self.write(PHASER_ADDR_SPI_CFG,
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self.write8(PHASER_ADDR_SPI_SEL, select)
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self.write8(PHASER_ADDR_SPI_DIV, div)
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self.write8(PHASER_ADDR_SPI_CFG,
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(offline << 0) | (end << 1) | (clk_phase << 2) |
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(clk_polarity << 3) | (half_duplex << 4) |
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(lsb_first << 5))
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@kernel
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def spi_write(self, data):
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self.write(PHASER_ADDR_SPI_DATW, data)
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self.write8(PHASER_ADDR_SPI_DATW, data)
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@kernel
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def spi_read(self):
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return self.read(PHASER_ADDR_SPI_DATR)
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return self.read8(PHASER_ADDR_SPI_DATR)
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@kernel
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def dac_write(self, addr, data):
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@ -194,12 +237,45 @@ class Phaser:
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self.spi_write(0)
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delay_mu(t_xfer)
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data = self.spi_read()
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delay(10*us)
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delay(10*us) # slack
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self.spi_cfg(select=PHASER_SEL_ATT0 << ch, div=div, end=1)
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self.spi_write(data)
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delay_mu(t_xfer)
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return data
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@kernel
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def trf_write(self, ch, data, readback=False):
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div = 30 # 50 ns min period
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t_xfer = self.core.seconds_to_mu((8 + 1)*(div + 2)*4*ns)
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read = 0
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if readback:
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clk_phase = 1
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else:
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clk_phase = 0
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end = 0
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for i in range(4):
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if i == 0 or i == 3:
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if i == 3:
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end = 1
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self.spi_cfg(select=PHASER_SEL_TRF0 << ch, div=div,
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lsb_first=1, clk_phase=clk_phase, end=end)
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self.spi_write(data & 0xff)
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data >>= 8
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delay_mu(t_xfer)
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if readback:
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read >>= 8
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read |= self.spi_read() << 24
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delay(10*us) # slack
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return read
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@kernel
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def trf_read(self, ch, addr, cnt_mux_sel=0) -> TInt32:
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self.trf_write(ch, 0x80000008 | (addr << 28) | (cnt_mux_sel << 27))
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# single clk pulse to start readback
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self.spi_cfg(select=PHASER_SEL_TRF0 << ch, div=30, end=1, clk_polarity=1)
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self.spi_cfg(select=PHASER_SEL_TRF0 << ch, div=30, end=1, clk_polarity=0)
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return self.trf_write(ch, 0x00000008, readback=True)
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@kernel
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def set_frequency_mu(self, ch, osc, ftw):
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addr = ((self.channel_base + 1 + ch) << 8) | (osc << 1)
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@ -37,15 +37,13 @@ class Phaser(Module):
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n_channels = 2
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n_samples = 8
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n_bits = 14
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body = [Signal(n_channels*2*n_bits, reset_less=True)
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for i in range(n_samples)]
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i_sample = Signal(max=n_samples)
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body = Signal(n_samples*n_channels*2*n_bits, reset_less=True)
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self.sync.rio_phy += [
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If(self.ch0.dds.valid, # & self.ch1.dds.valid,
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Array(body)[i_sample].eq(Cat(
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self.ch0.dds.o.q[2:], self.ch0.dds.o.i[2:],
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self.ch1.dds.o.q[2:], self.ch1.dds.o.i[2:])),
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i_sample.eq(i_sample + 1),
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# recent sample, ch0, i first
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Cat(body).eq(Cat(self.ch0.dds.o.i[2:], self.ch0.dds.o.q[2:],
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self.ch1.dds.o.i[2:], self.ch1.dds.o.q[2:],
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body)),
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),
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]
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@ -57,11 +55,6 @@ class Phaser(Module):
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Cat(self.intf.data[:-1]).eq(Cat(self.serializer.data[:-1])),
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self.serializer.data[-1].eq(self.intf.data[-1]),
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]
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self.sync.rio_phy += [
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If(self.serializer.stb,
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i_sample.eq(0),
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),
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]
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header = Record([
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("we", 1),
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