forked from M-Labs/artiq
phaser: refactor link
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@ -1,6 +1,6 @@
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.io import DifferentialOutput, DifferentialInput, DDROutput
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from migen.genlib.io import (DifferentialOutput, DifferentialInput,
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DDROutput, DDRInput)
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
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from artiq.gateware.rtio import rtlink
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@ -17,16 +17,18 @@ class SerDes(Module):
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* One return data lane at slower speed.
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* n_frame//2 - 1 marker bits are used to provide framing.
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* `n_frame` words per frame
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* `n_data` lanes
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* `t_clk` bits per clk cycle with pattern `d_clk`
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* `n_crc` CRC bits per frame
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* `n_frame` words per frame
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* `n_crc` CRC bits per frame for divisor poly `poly`
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"""
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# pins
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self.data = [Signal(2) for _ in range(n_data)]
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n_lanes = n_data - 2 # number of data lanes
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n_word = n_lanes*t_clk
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t_frame = t_clk*n_frame//2
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n_body = n_word*n_frame - (n_frame//2 + 1) - n_crc
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n_mosi = n_data - 2 # mosi lanes
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n_word = n_mosi*t_clk # bits per word
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t_frame = t_clk*n_frame # frame duration
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n_marker = n_frame//2 + 1
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n_body = n_word*n_frame - n_marker - n_crc
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t_miso = 0 # miso sampling latency TODO
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# frame data
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@ -39,11 +41,11 @@ class SerDes(Module):
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# # #
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self.submodules.crc = LiteEthMACCRCEngine(
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data_width=2*n_lanes, width=n_crc, polynom=poly)
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data_width=2*n_mosi, width=n_crc, polynom=poly)
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words_ = []
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j = 0
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# last, LSB to first, MSB
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# build from LSB to MSB because MSB first
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for i in range(n_frame): # iterate over words
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if i == 0: # data and checksum
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k = n_word - n_crc
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@ -64,65 +66,60 @@ class SerDes(Module):
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self.comb += words.eq(words_)
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clk = Signal(t_clk, reset=d_clk)
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i = Signal(max=t_frame)
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i = Signal(max=t_frame//2)
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# big shift register for clk and mosi
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sr = [Signal(t_frame*2 - n_crc//n_lanes, reset_less=True)
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for i in range(n_lanes)]
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sr = [Signal(t_frame - n_crc//n_mosi, reset_less=True)
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for i in range(n_mosi)]
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assert len(Cat(sr)) == len(words)
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# DDR bits for each register
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ddr_data = Cat([sri[-2] for sri in sr], [sri[-1] for sri in sr])
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self.comb += [
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self.stb.eq(i == t_frame - 1),
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# LiteETHMACCRCEngine takes data LSB first
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self.crc.data[::-1].eq(ddr_data),
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]
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miso = Signal()
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crc_data = [sri[-2] for sri in sr] + [sri[-1] for sri in sr]
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miso_sr = Signal(t_frame, reset_less=True)
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miso_sr_next = Signal.like(miso_sr)
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self.comb += [
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self.stb.eq(i == t_frame//2 - 1),
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# LiteETHMACCRCEngine takes data LSB first
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self.crc.data.eq(Cat(reversed(crc_data))),
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miso_sr_next.eq(Cat(self.data[-1], miso_sr)),
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[di.eq(sri[-2:]) for di, sri in zip(self.data, [clk] + sr)],
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]
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self.sync.rio_phy += [
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# shift everything by two bits
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clk.eq(Cat(clk[-2:], clk)),
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[sri[2:].eq(sri) for sri in sr],
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[sri.eq(Cat(sri[-2:], sri)) for sri in [clk] + sr],
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miso_sr.eq(miso_sr_next),
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self.crc.last.eq(self.crc.next),
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miso_sr.eq(Cat(miso, miso_sr)),
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i.eq(i + 1),
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If(self.stb,
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i.eq(0),
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clk.eq(clk.reset),
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self.crc.last.eq(0),
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# transpose, load
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Cat(sr).eq(Cat(words[mm::n_lanes] for mm in range(n_lanes))),
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self.readback.eq(Cat([miso_sr[int(round(t_miso + i*t_clk/2.))]
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for i in range(n_frame)])),
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[sri.eq(Cat(words[i::n_mosi])) for i, sri in enumerate(sr)],
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# unload miso
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self.readback.eq(Cat([miso_sr_next[t_miso + i*t_clk]
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for i in range(n_frame)])),
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),
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If(i == t_frame - 2,
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If(i == t_frame//2 - 2,
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# inject crc for the last cycle
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ddr_data.eq(self.crc.next),
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Cat(crc_data).eq(self.crc.next),
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),
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]
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self.comb += [
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self.data[0].eq(clk[-2:]),
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[di.eq(sri[-2:]) for di, sri in zip(self.data[1:-1], sr)],
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miso.eq(self.data[-1]),
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]
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class SerInterface(Module):
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def __init__(self, pins, pins_n):
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n_data = 1 + len(pins.mosi) + 1
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self.data = [Signal(2) for _ in range(n_data)]
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clk_ddr = Signal()
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miso_reg = Signal()
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self.specials += [
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DDROutput(self.data[0][-1], self.data[0][-2],
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clk_ddr, ClockSignal("rio_phy")),
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DifferentialOutput(clk_ddr, pins.clk, pins_n.clk),
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DifferentialInput(pins.miso, pins_n.miso, miso_reg),
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MultiReg(miso_reg, self.data[-1], "rio_phy"),
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]
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for i in range(len(pins.mosi)):
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self.data = [Signal(2) for _ in range(2 + len(pins.mosi))]
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for d, pp, pn in zip(self.data,
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[pins.clk] + list(pins.mosi),
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[pins_n.clk] + list(pins_n.mosi)):
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ddr = Signal()
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self.specials += [
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DDROutput(self.data[-1], self.data[-2], ddr, ClockSignal("rio_phy")),
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DifferentialOutput(ddr, pins.mosi[i], pins_n.mosi[i]),
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DDROutput(d[-1], d[-2], ddr, ClockSignal("rio_phy")),
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DifferentialOutput(ddr, pp, pn),
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]
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ddr = Signal()
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self.specials += [
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DifferentialInput(pins.miso, pins_n.miso, ddr),
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DDRInput(ddr, self.data[-1][-1], self.data[-1][-2],
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ClockSignal("rio_phy")),
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]
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@ -9,7 +9,7 @@ class Phaser(Module):
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self.config = rtlink.Interface(
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rtlink.OInterface(data_width=8, address_width=8,
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enable_replace=False),
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rtlink.IInterface(data_width=8))
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rtlink.IInterface(data_width=10))
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self.data = rtlink.Interface(
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rtlink.OInterface(data_width=32, address_width=8,
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enable_replace=True))
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@ -31,8 +31,9 @@ class Phaser(Module):
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])
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n_channels = 2
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n_samples = 8
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body = [[(Signal(14), Signal(14)) for i in range(n_channels)]
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for j in range(n_samples)]
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n_bits = 14
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body = [[(Signal(n_bits), Signal(n_bits))
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for i in range(n_channels)] for j in range(n_samples)]
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assert len(Cat(header.raw_bits(), body)) == \
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len(self.serializer.payload)
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self.comb += self.serializer.payload.eq(Cat(header.raw_bits(), body))
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