Sebastien Bourdeauducq
|
c5fe2799cf
|
conda: bump misoc
|
2017-08-31 13:44:31 +08:00 |
Sebastien Bourdeauducq
|
b609366c6f
|
runtime: fix Rust types in RTIO
Previous code assumed all RTIO registers were u32, but this was changed
by misoc c5edcd08.
|
2017-08-31 13:42:32 +08:00 |
Sebastien Bourdeauducq
|
44edba0c65
|
firmware: add placeholder code for HMC830/7043 initialization
|
2017-08-31 13:35:47 +08:00 |
Sebastien Bourdeauducq
|
9edff2c520
|
remote_csr: interpret length as CSR size, not number of bus words
|
2017-08-31 13:34:48 +08:00 |
Sebastien Bourdeauducq
|
0a5904bbaa
|
firmware: support for multiple JESD DACs
|
2017-08-31 13:05:48 +08:00 |
Sebastien Bourdeauducq
|
a4144a07c4
|
sayma_amc: add converter SPI config defines
|
2017-08-31 13:04:38 +08:00 |
Sebastien Bourdeauducq
|
bacf8a1614
|
style
|
2017-08-31 12:52:09 +08:00 |
Sebastien Bourdeauducq
|
5a041c24f3
|
conda: bump misoc
|
2017-08-31 12:17:52 +08:00 |
Sebastien Bourdeauducq
|
d92cca9712
|
artiq_flash: fix target_file handling
|
2017-08-31 12:16:52 +08:00 |
Sebastien Bourdeauducq
|
e652221221
|
conda: bump migen and misoc
|
2017-08-31 11:50:32 +08:00 |
Sebastien Bourdeauducq
|
ad0a940e2d
|
sayma_rtm: hook up DAC SPI
|
2017-08-31 11:48:54 +08:00 |
Sebastien Bourdeauducq
|
f765dc50de
|
sayma_rtm: do not keep DACs in reset
|
2017-08-31 11:44:33 +08:00 |
Sebastien Bourdeauducq
|
a67659338d
|
sayma: clean up serwb comments
|
2017-08-31 11:42:01 +08:00 |
Florent Kermarrec
|
660f9856ec
|
gateware/serwb: add test for phy initialization
|
2017-08-30 17:59:10 +02:00 |
Florent Kermarrec
|
9650233007
|
gateware/serwb: change serdes clock domain to serwb_serdes
|
2017-08-30 15:44:44 +02:00 |
Florent Kermarrec
|
32ca51faee
|
gateware/targets/sayma_amc_standalone/rtm: use new serwb modules
|
2017-08-30 15:25:20 +02:00 |
Florent Kermarrec
|
41d57d64f6
|
gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window
|
2017-08-30 14:40:11 +02:00 |
Florent Kermarrec
|
9ba50098a8
|
gateware/test/serwb: use unittest for in test_etherbone
|
2017-08-29 17:31:01 +02:00 |
Florent Kermarrec
|
7d7f6be7ce
|
gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction
|
2017-08-29 16:41:29 +02:00 |
Florent Kermarrec
|
60ad36e7d6
|
gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready
|
2017-08-29 13:43:26 +02:00 |
Florent Kermarrec
|
89558e2653
|
gateware/serwb: for the initial version set delay in the center of the valid sampling window and don't use phase detectors
we'll use phase detectors later when it will be working reliably for both artix7 and kintex ultrascale
|
2017-08-29 13:38:52 +02:00 |
Sebastien Bourdeauducq
|
26a11a296c
|
sayma_rtm: drive DAC control signals
|
2017-08-26 16:57:02 -07:00 |
Sebastien Bourdeauducq
|
d609c67cbd
|
sayma_rtm: set clock mux pins
|
2017-08-26 16:48:10 -07:00 |
Sebastien Bourdeauducq
|
9194402ea5
|
sayma_rtm: expose HMC SPI bus
|
2017-08-26 16:31:31 -07:00 |
Sebastien Bourdeauducq
|
dbc12540da
|
sayma_amc: register RTM CSR regions from CSV
|
2017-08-26 14:48:11 -07:00 |
Sebastien Bourdeauducq
|
54c75d3274
|
sayma_rtm: use CSR infrastructure, generate CSR CSV
|
2017-08-23 17:19:53 -04:00 |
Sebastien Bourdeauducq
|
668450db26
|
sayma_amc: add serwb
|
2017-08-21 18:11:29 -04:00 |
Sebastien Bourdeauducq
|
0459a70cf6
|
sayma_amc: cleanup, fix RTM UART forwarding
|
2017-08-21 16:49:42 -04:00 |
Sebastien Bourdeauducq
|
1f2b373d09
|
sayma_rtm: remove unnecessary serwb_control
|
2017-08-21 16:37:13 -04:00 |
Sebastien Bourdeauducq
|
bfea297279
|
targets: add Sayma RTM
|
2017-08-21 15:58:01 -04:00 |
Sebastien Bourdeauducq
|
53c7f92fdc
|
serwb: add __init__.py and expose submodules
|
2017-08-21 15:57:43 -04:00 |
Sebastien Bourdeauducq
|
dac3a78b75
|
serwb: style, use migen, fix imports
|
2017-08-21 12:35:59 -04:00 |
Florent Kermarrec
|
da90a0fa12
|
Add test for Etherbone
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ec62242659910ad1726beb00ff15b3f0a406615
|
2017-08-21 12:31:49 -04:00 |
Florent Kermarrec
|
44dc76e42e
|
Add serial Wishbone bridge
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
|
2017-08-21 12:22:05 -04:00 |
Sebastien Bourdeauducq
|
d6b624dfbe
|
sayma_amc: connect RTM serial and second serial
|
2017-08-20 19:01:55 -04:00 |
Sebastien Bourdeauducq
|
e94d0803e1
|
artiq_flash: fix Sayma load addresses
|
2017-08-20 18:21:36 -04:00 |
Sebastien Bourdeauducq
|
261b6fb42e
|
artiq_flash: fix AMC_DR_LEN
|
2017-08-20 18:20:51 -04:00 |
Sebastien Bourdeauducq
|
9f4c9fc14b
|
artiq_flash: Sayma support
|
2017-08-20 17:23:56 -04:00 |
Sebastien Bourdeauducq
|
bee4902323
|
add Sayma AMC standalone target
|
2017-08-20 11:47:45 -04:00 |
Sebastien Bourdeauducq
|
ac83bfbd8e
|
runtime: add support for targets without SPI flash
|
2017-08-20 11:28:57 -04:00 |
Sebastien Bourdeauducq
|
1dab7df846
|
kc705_sma_spi: fix permissions
|
2017-08-20 10:54:24 -04:00 |
Robert Jördens
|
2a91b6996f
|
doc: update proxy bitstream url
|
2017-08-15 14:34:27 -06:00 |
Robert Jördens
|
34ddda7a0c
|
conda: use single-tap proxy bitstreams
|
2017-08-15 14:30:53 -06:00 |
Sebastien Bourdeauducq
|
8459cfe8db
|
firmware: remove unnecessary git_describe rust-cfg
|
2017-08-15 08:14:17 -06:00 |
mntng
|
ea135f9d06
|
add unittest for artiq_compile and ELF artiq_run (#455)
|
2017-08-15 08:13:11 -06:00 |
Sebastien Bourdeauducq
|
cf1de4b26a
|
test_spi: convert to Unix EOL
|
2017-08-04 11:48:20 +08:00 |
Robert Jördens
|
7085c1cccb
|
RELEASE_NOTES: clarify time/date
|
2017-08-03 13:56:15 +02:00 |
Robert Jördens
|
bc2d9ef818
|
Merge pull request #809 from cjbe/epoch_time
master: use epoch time for timestamps (closes #726)
|
2017-08-03 12:55:23 +02:00 |
Robert Jördens
|
dd6c48fed2
|
Merge branch 'master' into epoch_time
|
2017-08-03 12:55:01 +02:00 |
Chris Ballance
|
cc289dd3a0
|
master: store run_time and start_time as doubles
|
2017-08-03 10:41:57 +01:00 |