Commit Graph

3214 Commits

Author SHA1 Message Date
b83b113f3c gui/moninj: make widgets look less like buttons 2016-03-03 10:48:17 +08:00
0c97043a20 gateware/nist_clock: pin assignment corrections from David Leibrandt 2016-03-03 10:03:49 +08:00
d3f36ce784 kc705: add false paths for ethernet phy
* vivado prefers rsys_clk over sys_clk (despite the assignment hierarchy)
  (We need DONT_TOUCH and/or KEEP verilog annotations to fix this)
2016-03-02 19:56:24 +01:00
9969cd85de ad53xx: ldac may be none 2016-03-02 15:50:02 +01:00
f5dee455f5 test/worker: test exception logging 2016-03-02 17:12:22 +08:00
763a4d3011 rpctool: use pprint in interactive mode 2016-03-02 11:47:34 +08:00
d0d50d74eb rpctool: interactive mode 2016-03-02 11:45:51 +08:00
946bd84b58 protocols/pc_rpc: support retrieving selected target 2016-03-02 11:45:31 +08:00
1e4bccae20 ad53xx: add 2016-03-02 00:12:01 +01:00
162ecdd574 spi: cleanup, add frequency_to_div() 2016-03-02 00:11:17 +01:00
d973eb879f coredevice.spi: docstring fix 2016-03-01 22:42:00 +01:00
f754d2c117 Merge branch 'spimaster'
* spimaster: (52 commits)
  runtime/rtio: rtio_process_exceptional_status() has only one user
  coredevice.spi, doc/manual: add spi
  kc705: move ttl channels together again, update doc
  runtime: rt2wb_input -> rtio_input_data
  examples/tdr: adapt to compiler changes
  bridge: really fix O/OE
  runtime: define constants for ttl addresses
  coredevice.ttl: fix sensitivity
  bridge: fix ttl o/oe addresses
  runtime: refactor ttl*()
  rtio: rm rtio_write_and_process_status
  coredevice.spi: unused import
  rt2wb, exceptions: remove RTIOTimeout
  gateware.spi: delay only writes to data register, update doc
  nist_clock: disable spi1/2
  runtime/rt2wb: use input/output terminology and add (async) input
  examples: update device_db for nist_clock spi
  gateware.spi: rework wb bus sequence
  nist_clock: rename spi*.ce to spi*.cs_n
  nist_clock: add SPIMasters to spi buses
  ...
2016-03-01 22:08:08 +01:00
5ba753425d runtime/rtio: rtio_process_exceptional_status() has only one user 2016-03-01 21:38:51 +01:00
0456169558 coredevice.spi, doc/manual: add spi 2016-03-01 21:29:09 +01:00
2cc1dfaee3 kc705: move ttl channels together again, update doc 2016-03-01 19:40:32 +01:00
f30dc4b39e runtime: rt2wb_input -> rtio_input_data 2016-03-01 19:22:42 +01:00
baf7b0dcf2 examples/tdr: adapt to compiler changes 2016-03-01 19:04:03 +01:00
81b35be574 bridge: really fix O/OE 2016-03-01 18:49:04 +01:00
135643e3a6 runtime: define constants for ttl addresses 2016-03-01 18:22:42 +01:00
3aebbbdb61 coredevice.ttl: fix sensitivity 2016-03-01 18:22:03 +01:00
6f9656dcbe bridge: fix ttl o/oe addresses 2016-03-01 18:19:06 +01:00
8adef12781 runtime: refactor ttl*()
* remove rt2wb_output
* remove ttl_*() ttl.c ttl.h
* use rtio_output() and rtio_input_timestamp()
* adapt coredevice/compiler layer
* adapt bridge to not artiq_raise_from_c()
2016-03-01 16:36:59 +01:00
aa10791ddf rtio: rm rtio_write_and_process_status 2016-03-01 15:40:35 +01:00
29776fae3f coredevice.spi: unused import 2016-03-01 15:38:40 +01:00
324660ab40 rt2wb, exceptions: remove RTIOTimeout
Assume that rt2wb transactions either collide and are then
reported (https://github.com/m-labs/artiq/issues/308) or that
they complete and the delay with which they complete does not matter.

If a transaction is ack'ed with a delay because the WB core's downstream
logic is busy, that may lead to a later collision with another WB
transaction.
2016-03-01 14:44:07 +01:00
c2fe9a08ae gateware.spi: delay only writes to data register, update doc 2016-03-01 14:14:38 +01:00
whitequark
7e16da4a77 transforms.llvm_ir_generator: ignore assignments of None (fixes #309). 2016-03-01 12:26:42 +00:00
c7d48a1765 coredevice/TTLOut: add dummy output function 2016-03-01 19:03:10 +08:00
18efca0f0a Merge branch 'master' of github.com:m-labs/artiq 2016-03-01 14:49:16 +08:00
b0526c3354 protocols/pipe_ipc: fix resource leak on Windows 2016-03-01 14:49:04 +08:00
whitequark
dc70029b91 transforms.asttyped_rewriter: set loc for ForT (fixes #302). 2016-03-01 05:22:12 +00:00
f2ec8692c0 nist_clock: disable spi1/2 2016-03-01 01:52:46 +01:00
7d7a710a56 runtime/rt2wb: use input/output terminology and add (async) input 2016-03-01 00:35:56 +01:00
764795a8fe examples: update device_db for nist_clock spi 2016-02-29 22:32:53 +01:00
da22ec73df gateware.spi: rework wb bus sequence 2016-02-29 22:22:08 +01:00
12252abc8f nist_clock: rename spi*.ce to spi*.cs_n 2016-02-29 22:21:18 +01:00
7ef21f03b9 nist_clock: add SPIMasters to spi buses 2016-02-29 22:19:39 +01:00
8fa98f6486 doc: use term 'gateware'
FPGA newcomers are not used to the term 'bitstream'. To insist that this file
is the result of the gateware compilation and thus the binary FPGA format,
add the term 'gateware' as a prefix.
2016-02-29 20:50:45 +01:00
7ab7f7d75d Merge branch 'master' into spimaster
* master:
  artiq_flash: use term 'gateware'
  targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
  doc: insist that output() must be called on TTLInOut. Closes #297
  doc: update install instructions
  coredevice: do not give up on UTF-8 errors in log. Closes #300
  use m-labs setup for defaults
  fix indentation
2016-02-29 20:47:52 +01:00
6dd1eb2e92 artiq_flash: use term 'gateware' 2016-02-29 20:45:41 +01:00
6c899e6ba6 runtime/rtio: fix rtio_input_wait(), add RTIOTimeout 2016-02-29 19:49:15 +01:00
16537d347e coredevice.spi: cleanup 2016-02-29 19:48:26 +01:00
ecedbbef4c runtime/ttl: use rtio_output and rtio_input_wait 2016-02-29 19:20:07 +01:00
5dae9f8aa8 runtime: refactor rt2wb/dds 2016-02-29 19:16:29 +01:00
d3c94827eb runtime/ttl: simplify ttl_get() a bit 2016-02-29 17:58:54 +01:00
e11366869d coredevice/spi: clean up api 2016-02-29 17:54:42 +01:00
5fad570f5e targets/kc705-nist_clock: add clock generator on LA32 for testing purposes 2016-03-01 00:35:26 +08:00
dd570720ac gateware.spi: ack only in cycles 2016-02-29 17:29:37 +01:00
a1e1f2b387 doc: insist that output() must be called on TTLInOut. Closes #297 2016-03-01 00:28:40 +08:00
d0d56bd3fe doc: update install instructions 2016-03-01 00:19:55 +08:00