591507a7c0
Merge pull request #1774 from m-labs/fastino-cic
...
Fastino cic
2021-10-28 17:44:20 +02:00
5a5b0cc7c0
fastino: expand docs
2021-10-28 15:19:48 +00:00
69cddc6b86
rtio_clocking: add warnings for unsupported rtio_clock settings ( #1773 )
2021-10-28 16:34:22 +08:00
9b1d7e297d
runtime: clock input specification improvements
...
closes #1735
2021-10-28 16:21:51 +08:00
1ff474893d
Revert "fastino: make driver filter order configurable"
...
This reverts commit 10c37b87ec
2021-10-28 06:29:56 +00:00
10c37b87ec
fastino: make driver filter order configurable
2021-10-27 20:24:58 +00:00
c940f104f1
artiq_flash: fix gateware header not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
0aa8a739aa
sayma_rtm: fix RTM firmware not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
d5fa3d131a
cargo.lock: update libc version for libfringe
2021-10-16 17:42:24 +08:00
6d3164a912
riscv: print mtval on panic
2021-10-16 17:42:24 +08:00
46326716fd
runtime: bump libfringe, impl ecall abi
...
See libfringe PR: M-Labs/libfringe#1
2021-10-16 17:42:24 +08:00
0a59c889de
satman/kern: init locked PMP on startup
2021-10-16 17:42:24 +08:00
27a7a96626
runtime: setup pmp + transfer to user
2021-10-16 17:42:24 +08:00
a0bf11b465
riscv: impl pmp
2021-10-16 17:42:24 +08:00
790a20edf6
linker: generate stack guard + symbol
2021-10-16 17:42:24 +08:00
fanmingyu212
178a86bcda
master: add an argument to set an experiment subdirectory
...
Signed-off-by: Mingyu Fan <mingyufan@ucsb.edu>
2021-10-15 16:54:31 +08:00
fbd5c70250
Revert "runtime: expose rint from libm"
...
Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6
2021-10-11 08:12:58 +08:00
35d21c98d3
Revert "runtime: expose rint from libm"
...
Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6
2021-10-11 08:12:04 +08:00
17c283d091
runtime: expose rint from libm
2021-10-10 20:40:56 +08:00
f5100702f6
runtime: expose rint from libm
2021-10-10 20:40:17 +08:00
3c1cbf47d2
phaser: add more slack during init. Closes #1757
2021-10-10 16:18:55 +08:00
3f6bf33298
fastino: add interpolator support
2021-10-08 15:47:07 +00:00
97909d7619
remove old compiler, add nac3 dependency (WIP)
2021-10-08 00:30:27 +08:00
59065c4663
alloc_list: support alloc w/ large align
...
Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
2021-10-07 12:38:03 +08:00
1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path ( #1760 )
2021-10-07 08:19:38 +08:00
a8333053c9
sinara_tester: add device_db and test selection CLI options
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-27 17:44:50 +08:00
3ed10221d8
compiler: remove big-endian support. Closes #1590
2021-09-13 13:40:24 +08:00
e8a7a8f41e
compiler: work around idiotic windoze behavior that causes conda ld.lld not to be found
2021-09-13 10:40:54 +08:00
ffb1e3ec2d
wavesynth: np.int is deprecated
2021-09-13 07:02:35 +08:00
2d79d824f9
firmware: remove minor or1k leftovers
2021-09-12 20:03:37 +08:00
a573dcf3f9
board_misoc/build: use rv32 as target arg
...
The original rv64 argument was only to match the misoc counterpart.
2021-09-10 14:11:23 +08:00
448974fe11
runtime/main: cleanup
2021-09-10 13:59:53 +08:00
b091d8cb66
kernel: flush cache before mod_init
...
This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
2021-09-10 13:25:12 +08:00
5394d04669
test_spi: add delay
2021-09-10 13:25:12 +08:00
b8ed5a0d91
alloc: fix alignment for riscv32 arch
2021-09-10 13:25:12 +08:00
2213e7ffac
ksupp/rtio/exception: fix timestamp
2021-09-10 13:25:12 +08:00
09ffd9de1e
dma: fix timestamp fetch
2021-09-10 13:25:12 +08:00
051a14abf2
rtio/dma: fix endianness
2021-09-10 13:25:12 +08:00
c6ba0f3cf4
ksupport: fix dma cslice (ffi)
2021-09-10 13:25:12 +08:00
c812a837ab
runtime: enlarge stack size
2021-09-10 13:25:12 +08:00
a596db404d
satman: fix cargo xbuild sysroot
2021-09-10 13:25:12 +08:00
4fab267593
cargo: std dependency hack
2021-09-10 13:25:12 +08:00
dcbd9f905c
cargo: use cargo xbuild
2021-09-10 13:25:12 +08:00
9f6b3f6014
firmware: clarify target triple
...
The lack of compressed instruction support can be inferred from the target triple, literally.
2021-09-10 13:25:12 +08:00
4619a33db4
test: remove broken array return tests
...
Removed test cases that do not respect lifetime/scope constraint.
See discussion in artiq-zynq repo: M-Labs/artiq-zynq#119
Referred to the patch from @dnadlinger. 5faa30a837
2021-09-10 13:25:12 +08:00
5985f7efb5
syscall: lower nowrite to inaccessiblememonly
...
In the origin implementation, the `nowrite` flag literally means not writing memory at all.
Due to the usage of flags on certain functions, it results in the same issues found in artiq-zynq after optimization passes. (M-Labs/artiq-zynq#119 )
A fix wrote by @dnadlinger can resolve this issue. (c1e46cc7c8
2021-09-10 13:25:12 +08:00
6db7280b09
flake: board package WIP
2021-09-10 13:25:12 +08:00
d8ac429059
dyld: streamline lib.rs
...
Only riscv32 is supported anyway, no need to have excessive architecture check.
2021-09-10 13:25:12 +08:00
798774192d
slave_fpga/bootloader: read in little endian
2021-09-10 13:25:12 +08:00
eecd825d23
firmware: suppress warning
2021-09-10 13:25:12 +08:00
1da0554a49
pcr: purge
2021-09-10 13:25:12 +08:00
5d0a8cf9ac
llvm_ir_gen: fix indent
2021-09-10 13:25:12 +08:00
70507e1b72
Cargo.lock: update
2021-09-10 13:25:12 +08:00
c113cd6bf5
libfringe: bump
2021-09-10 13:25:12 +08:00
61b0170a12
firmware: purge or1k
2021-09-10 13:25:12 +08:00
af263ffe1f
ksupport: fix rpc, cache signature (FFI)
...
The reason of the borrow stuff is explained in M-Labs/artiq-zynq#76 (artiq-zyna repo).
As for `cache_get()`, compiler will perform stack allocation to pre-allocate the returned structure, and pass to cache_get alongside the `key`.
However, ksupport fails to recognize the passed memory, so it will always assume the passed memory as the key.
2021-09-10 13:25:12 +08:00
a833974b50
analyzer: fix endianness
2021-09-10 13:25:12 +08:00
d623acc29d
llvm_ir_gen: fix now with now_pinning & little-endian target
2021-09-10 13:25:12 +08:00
8fa47b8119
rpc: enforce alignment
2021-09-10 13:25:12 +08:00
de0f2d4a28
firmware: adopt endianness protocol in artiq-zynq
...
Related:
artiq-zynq: M-Labs/artiq-zynq#126
artiq: #1588
2021-09-10 13:25:12 +08:00
9afe63c08a
ksupport: fix proto_artiq dependency
2021-09-10 13:25:12 +08:00
29a2f106d1
ksupport: replace asm with llvm_asm
2021-09-10 13:25:12 +08:00
b30ed75e69
kernel.ld: load elf header and prog headers
...
ld.lld has a habit of not putting the headers under any load sections.
However, the headers are needed by libunwind to handle exception raised by the kernel.
Creating PT_LOAD section with FILEHDR and PHDRS solves this issue. Other PHDRS are also specified as linkers (not limited to ld.lld) will not create additional unspecified headers even when necessary.
2021-09-10 13:25:12 +08:00
279593f984
ksupport.ld: merge sbss with bss
2021-09-10 13:25:12 +08:00
1ba8c8dfee
runtime: remove irq again
2021-09-10 13:25:12 +08:00
3d629006df
makefiles: revert byte-swaps
2021-09-10 13:25:12 +08:00
7542105f0f
board_misoc: remove pcr
...
VexRiscv seems to not support additional hardware performance counter, at least I have not seen any documentation on how to use it.
2021-09-10 13:25:12 +08:00
01ca114c66
runtime: remove irq dependency
2021-09-10 13:25:12 +08:00
36171f2c61
runtime: remove inaccurate sp on panic
2021-09-10 13:25:12 +08:00
01e357e5d3
ksupport.ld: reduce load section alignment
2021-09-10 13:25:12 +08:00
f77b607b56
compiler: generate symbols
2021-09-10 13:25:12 +08:00
1293e0750e
ld, makefiles: use ld.lld
2021-09-10 13:25:12 +08:00
fc42d053d9
kernel: use vexriscv
2021-09-10 13:25:12 +08:00
1b516b16e2
targets: default to vexriscv cpu
2021-09-10 13:25:12 +08:00
e8fe8409b2
libartiq_support: compatibility with recent stable rustc
2021-09-10 13:25:12 +08:00
cabe5ace8e
compiler: remove DebugInfoEmitter for now
...
Causes problems with LLVM 9 and not needed at first.
2021-09-10 13:25:12 +08:00
6629a49e86
compiler: use LLVM binutils/linker for Arm as well
...
Previously we kept GNU Binutils because they are less of a pain to support
on Windoze - the source of so many problems - but with RISC-V we need to
update LLVM anyway.
2021-09-10 13:25:12 +08:00
43d120359d
compiler: switch to upstream llvmlite and RISC-V target
2021-09-10 13:25:12 +08:00
5656e52581
remove profiler
2021-09-10 13:25:12 +08:00
1b8b4baf6a
ksupport: fix panic, libc, unwind
2021-09-10 13:25:12 +08:00
905330b0f1
ksupport: handle riscv exceptions
2021-09-10 13:25:12 +08:00
50a62b3d42
liballoc: change align to 16 bytes
2021-09-10 13:25:12 +08:00
7f0bc9f7f0
runtime/makefile: specify emulation, flip endianness
2021-09-10 13:25:12 +08:00
c42adfe6fd
runtime.ld: merge .sbss & .bss
2021-09-10 13:25:12 +08:00
f56152e72f
rust: fix dependencies
2021-09-10 13:25:12 +08:00
c800b6c8d3
runtime: update rust alloc, managed
2021-09-10 13:25:09 +08:00
e99061b013
runtime: add riscv
2021-09-10 13:23:22 +08:00
ecedec577c
runtime: impl riscv exception handling
2021-09-10 13:23:15 +08:00
252594a606
runtime: impl riscv panic handler
2021-09-10 13:20:31 +08:00
31bf17563c
personality: update from rust/panic_unwind
2021-09-10 13:20:31 +08:00
bfddd8a30f
libdyld: add riscv support
2021-09-10 13:20:31 +08:00
ad3037d0f6
libc: add minimal C types
2021-09-10 13:20:31 +08:00
daaf6c3401
libunwind: add rust interface
2021-09-10 13:20:31 +08:00
6d9cebfd42
satman: handle .sbss generation
2021-09-10 13:20:31 +08:00
96438c9da7
satman: make fbi big-endian
2021-09-10 13:20:31 +08:00
6535b2f089
satman: fix feature
2021-09-10 13:20:31 +08:00
45adaa1d98
satman: add riscv exception handling
2021-09-10 13:20:31 +08:00
869a282410
satman: use riscv
2021-09-10 13:20:31 +08:00
ebb9f298b5
proto_artiq: update alloc type path
2021-09-10 13:20:31 +08:00
97a0132f15
libio: update alloc type path
2021-09-10 13:20:31 +08:00
37ea863004
libio: pin failure version
2021-09-10 13:20:31 +08:00
3ff74e0693
bootloader: handle .sbss generation in .ld
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
448fe0e8cf
bootloader: fix panic
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
8294d7fea5
bootloader: swap endianness
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
13032272fd
bootloader: add rv32 exception handler
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
46102ee737
board_misoc: build vectors.S with rv64 target in misoc
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
b87ea79d51
rv32: rm irq & vexriscv-rust
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
9aee42f0f2
rv32/boot: remove hotswap
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
82b4052cd6
libboard_misoc: vexriscv integration
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
Leon Riesebos
2cf144a60c
ddb_template: edge counter keys correspond with according ttl keys
...
previously ttl_counter_0 and ttl_0 could be on completely different physical ttl output channels
with this change, ttl_0_counter (note the changed key format) is always on the same channel as ttl_0
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
2021-09-06 09:06:04 +08:00
4d7bd3ee32
phaser: fail init() if frame timestamp measurement times out
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-03 12:01:26 +02:00
075cb26dd7
phaser: rename get_next_frame_timestamp() to get_next_frame_mu()
...
and implement review comments (PR #1749 )
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-03 09:58:01 +02:00
7aebf02f84
phaser: docs: add reference to get_next_frame_timestamps(), fix typo
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-01 17:44:46 +02:00
61b44d40dd
phaser: add labels to debug init prints
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-01 17:43:30 +02:00
65f8a97b56
phaser: add helpers to align updates to the RTIO timeline
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-01 17:42:54 +02:00
SingularitySurfer
65f63e6927
fix suservo start
2021-08-19 07:38:48 +00:00
a53162d01d
tester: tweak suservo
...
* p gain 1 to get reasonable power
* refine testing instructions and comments
2021-08-19 09:17:14 +02:00
SingularitySurfer
4d21a72407
Implement SUServo tester.
2021-08-18 15:10:27 +00:00
Mikołaj Sowiński
898122f3e5
Added support for HVAMP_8CH ( #1741 )
2021-08-16 13:39:00 +08:00
420891ba54
syntax
2021-08-12 13:01:35 +08:00
9f94bc61ae
missing part of 477b1516d
2021-08-12 12:55:37 +08:00
c69a1316ad
compiler: stop using sys.version_info for parser
2021-08-12 12:52:24 +08:00
477b1516d3
remove profiler
2021-08-12 12:51:55 +08:00
67847f98f4
artiq_run: fix multiarch
2021-08-12 12:48:10 +08:00
7879d3630b
made kc705/gtx interface more similar to kasli/gtp
2021-08-10 18:53:52 +08:00
242dfae38e
kc705: fix DRTIO targets
2021-08-06 15:41:47 +08:00
5111132ef0
ICAP: prevent sayma from using it ( #1740 )
2021-08-06 15:08:30 +08:00
dc546630e4
kc705: DRTIO variants WIP
2021-08-06 14:41:41 +08:00
fd824f7ad0
ddb_template: print LED channel nos on Kasli v2
2021-08-05 17:29:38 +02:00
c9608c0a89
zotino: default div_read unified with ad53xx at 16, fix ad53xx doc
2021-08-05 17:42:11 +08:00
6b88ea563d
talk to ICAP primitive to restart gateware ( #1733 )
2021-08-05 17:00:31 +08:00
97e994700b
compiler: turn __repr__ into __str__ when sphinx is used. Closes #741
2021-08-05 11:32:20 +08:00
c3d765f745
ad9910: fix type annotations
2021-08-05 11:30:54 +08:00
53a98acfe4
artiq_flash: cleanup openocd handling, do not follow symlinks
...
Not following symlinks allows files to be added to OpenOCD via nixpkgs buildEnv.
2021-07-26 17:01:24 +08:00
30e5e06a33
moninj: fix read of incomplete data ( #1729 )
2021-07-22 17:56:38 +08:00
ebb67eaeee
applets: add length warning message on plot for plot_xy_hist and fix bug ( #1725 )
2021-07-19 15:45:48 +08:00
943a95e07a
applets: add data length warning message for plot_xy ( #1722 )
2021-07-19 15:14:15 +08:00
e996b5f635
applets: fix warning timing
2021-07-19 12:26:01 +08:00
4fb8ea5b73
artiq_flash: determine which firmware to flash by looking at filesystem
...
Closes #1719
2021-07-14 16:43:00 +08:00
5cd721c514
applets: add plot_hist dataset length mismatch warning ( #1718 )
2021-07-14 15:57:55 +08:00
Star Chen
6ce9c26402
GUI: add option to create new datasets ( #1716 )
2021-07-13 12:53:35 +08:00
2204fd2b22
adf5356: add delay to sync()
...
Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
2021-07-08 10:03:20 +08:00
b10d1bdd37
compiler: proper union find
...
The find implementation was not very optimized, and the unify function
did not consider tree height and may build some tall trees.
2021-07-07 09:22:16 +08:00
4ede58e44b
compiler: reduce calls to TypedTreeHasher
...
We need to check if our inference reached a fixed point. This is checked
using hash of the types in the AST, which is very slow. This patch
avoids computing the hash if we can make sure that the AST is definitely
changed, which is when we parse a new function.
For some simple programs with many functions, this can significantly
reduce the compile time by up to ~30%.
2021-07-07 09:22:16 +08:00
822e8565f7
compiler: supports kernel decorators with path
2021-07-02 17:01:31 +08:00
6fb31a7abb
compiler: allow empty list in quote
2021-07-02 15:16:19 +08:00
0806b67dbf
compiler: speedup list processing
2021-07-02 14:22:25 +08:00
f531af510c
compiler: fixed embedding annotation evaluation
2021-06-25 11:32:23 +08:00
c29a149d16
compiler: allows string annotation
...
According to PEP484, type hint can be a string literal for forward
references. With PEP563, type hint would be preserved in annotations in
string form.
2021-06-25 11:01:48 +08:00
Etienne Wodey
68268e3db8
docs: fix some formatting issues
...
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2021-06-23 20:29:43 +08:00
