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firmware: adopt endianness protocol in artiq-zynq

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Related:
artiq-zynq: M-Labs/artiq-zynq#126
artiq: #1588
This commit is contained in:
occheung 2021-08-24 16:56:05 +08:00
parent 9afe63c08a
commit de0f2d4a28
6 changed files with 25 additions and 25 deletions
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20
artiq/firmware/libio/proto.rs
View File

@ -1,6 +1,6 @@
#[cfg(feature = "alloc")]
use {core::str::Utf8Error, alloc::string::String};
use byteorder::{ByteOrder, NetworkEndian};
use byteorder::{ByteOrder, NativeEndian};
use ::{Read, Write, Error as IoError};
@ -29,21 +29,21 @@ pub trait ProtoRead {
fn read_u16(&mut self) -> Result<u16, Self::ReadError> {
let mut bytes = [0; 2];
self.read_exact(&mut bytes)?;
Ok(NetworkEndian::read_u16(&bytes))
Ok(NativeEndian::read_u16(&bytes))
}
#[inline]
fn read_u32(&mut self) -> Result<u32, Self::ReadError> {
let mut bytes = [0; 4];
self.read_exact(&mut bytes)?;
Ok(NetworkEndian::read_u32(&bytes))
Ok(NativeEndian::read_u32(&bytes))
}
#[inline]
fn read_u64(&mut self) -> Result<u64, Self::ReadError> {
let mut bytes = [0; 8];
self.read_exact(&mut bytes)?;
Ok(NetworkEndian::read_u64(&bytes))
Ok(NativeEndian::read_u64(&bytes))
}
#[inline]
@ -88,42 +88,42 @@ pub trait ProtoWrite {
#[inline]
fn write_u16(&mut self, value: u16) -> Result<(), Self::WriteError> {
let mut bytes = [0; 2];
NetworkEndian::write_u16(&mut bytes, value);
NativeEndian::write_u16(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_i16(&mut self, value: i16) -> Result<(), Self::WriteError> {
let mut bytes = [0; 2];
NetworkEndian::write_i16(&mut bytes, value);
NativeEndian::write_i16(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_u32(&mut self, value: u32) -> Result<(), Self::WriteError> {
let mut bytes = [0; 4];
NetworkEndian::write_u32(&mut bytes, value);
NativeEndian::write_u32(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_i32(&mut self, value: i32) -> Result<(), Self::WriteError> {
let mut bytes = [0; 4];
NetworkEndian::write_i32(&mut bytes, value);
NativeEndian::write_i32(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_u64(&mut self, value: u64) -> Result<(), Self::WriteError> {
let mut bytes = [0; 8];
NetworkEndian::write_u64(&mut bytes, value);
NativeEndian::write_u64(&mut bytes, value);
self.write_all(&bytes)
}
#[inline]
fn write_i64(&mut self, value: i64) -> Result<(), Self::WriteError> {
let mut bytes = [0; 8];
NetworkEndian::write_i64(&mut bytes, value);
NativeEndian::write_i64(&mut bytes, value);
self.write_all(&bytes)
}

18
artiq/firmware/libproto_artiq/rpc_proto.rs
View File

@ -1,7 +1,7 @@
use core::str;
use core::slice;
use cslice::{CSlice, CMutSlice};
use byteorder::{NetworkEndian, ByteOrder};
use byteorder::{NativeEndian, ByteOrder};
use io::{ProtoRead, Read, Write, ProtoWrite, Error};
use self::tag::{Tag, TagIterator, split_tag};
@ -69,13 +69,13 @@ unsafe fn recv_value<R, E>(reader: &mut R, tag: Tag, data: &mut *mut (),
let dest = slice::from_raw_parts_mut(data as *mut u8, length * 4);
reader.read_exact(dest)?;
let dest = slice::from_raw_parts_mut(data as *mut i32, length);
NetworkEndian::from_slice_i32(dest);
NativeEndian::from_slice_i32(dest);
},
Tag::Int64 | Tag::Float64 => {
let dest = slice::from_raw_parts_mut(data as *mut u8, length * 8);
reader.read_exact(dest)?;
let dest = slice::from_raw_parts_mut(data as *mut i64, length);
NetworkEndian::from_slice_i64(dest);
NativeEndian::from_slice_i64(dest);
},
_ => {
for _ in 0..length {
@ -109,13 +109,13 @@ unsafe fn recv_value<R, E>(reader: &mut R, tag: Tag, data: &mut *mut (),
let dest = slice::from_raw_parts_mut(data as *mut u8, length * 4);
reader.read_exact(dest)?;
let dest = slice::from_raw_parts_mut(data as *mut i32, length);
NetworkEndian::from_slice_i32(dest);
NativeEndian::from_slice_i32(dest);
},
Tag::Int64 | Tag::Float64 => {
let dest = slice::from_raw_parts_mut(data as *mut u8, length * 8);
reader.read_exact(dest)?;
let dest = slice::from_raw_parts_mut(data as *mut i64, length);
NetworkEndian::from_slice_i64(dest);
NativeEndian::from_slice_i64(dest);
},
_ => {
for _ in 0..length {
@ -204,8 +204,8 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
let mut data = (*ptr).elements;
writer.write_u8(tag.as_u8())?;
match tag {
// we cannot use NetworkEndian::from_slice_i32 as the data is not mutable,
// and that is not needed as the data is already in network endian
// we cannot use NativeEndian::from_slice_i32 as the data is not mutable,
// and that is not needed as the data is already in native endian
Tag::Bool => {
let slice = slice::from_raw_parts(data as *const u8, length);
writer.write_all(slice)?;
@ -243,8 +243,8 @@ unsafe fn send_value<W>(writer: &mut W, tag: Tag, data: &mut *const ())
let mut data = *buffer;
writer.write_u8(elt_tag.as_u8())?;
match elt_tag {
// we cannot use NetworkEndian::from_slice_i32 as the data is not mutable,
// and that is not needed as the data is already in network endian
// we cannot use NativeEndian::from_slice_i32 as the data is not mutable,
// and that is not needed as the data is already in native endian
Tag::Bool => {
let slice = slice::from_raw_parts(data as *const u8, length);
writer.write_all(slice)?;

2
artiq/firmware/runtime/analyzer.rs
View File

@ -51,7 +51,7 @@ fn worker(stream: &mut TcpStream) -> Result<(), IoError<SchedError>> {
};
debug!("{:?}", header);
stream.write_all("E".as_bytes())?;
stream.write_all("e".as_bytes())?;
header.write_to(stream)?;
if wraparound {
stream.write_all(&data[pointer..])?;

2
artiq/firmware/runtime/mgmt.rs
View File

@ -14,7 +14,7 @@ impl From<SchedError> for Error<SchedError> {
fn worker(io: &Io, stream: &mut TcpStream) -> Result<(), Error<SchedError>> {
read_magic(stream)?;
Write::write_all(stream, "E".as_bytes())?;
Write::write_all(stream, "e".as_bytes())?;
info!("new connection from {}", stream.remote_endpoint());
loop {

2
artiq/firmware/runtime/moninj.rs
View File

@ -123,7 +123,7 @@ fn connection_worker(io: &Io, _aux_mutex: &Mutex, _routing_table: &drtio_routing
let mut next_check = 0;
read_magic(&mut stream)?;
stream.write_all("E".as_bytes())?;
stream.write_all("e".as_bytes())?;
info!("new connection from {}", stream.remote_endpoint());
loop {

6
artiq/firmware/runtime/session.rs
View File

@ -1,6 +1,6 @@
use core::{mem, str, cell::{Cell, RefCell}, fmt::Write as FmtWrite};
use alloc::{vec::Vec, string::String};
use byteorder::{ByteOrder, NetworkEndian};
use byteorder::{ByteOrder, NativeEndian};
use io::{Read, Write, Error as IoError};
use board_misoc::{ident, cache, config};
@ -473,7 +473,7 @@ fn process_kern_queued_rpc(stream: &mut TcpStream,
_session: &mut Session) -> Result<(), Error<SchedError>> {
rpc_queue::dequeue(|slice| {
debug!("comm<-kern (async RPC)");
let length = NetworkEndian::read_u32(slice) as usize;
let length = NativeEndian::read_u32(slice) as usize;
host_write(stream, host::Reply::RpcRequest { async: true })?;
debug!("{:?}", &slice[4..][..length]);
stream.write_all(&slice[4..][..length])?;
@ -615,7 +615,7 @@ pub fn thread(io: Io, aux_mutex: &Mutex,
continue
}
}
match stream.write_all("E".as_bytes()) {
match stream.write_all("e".as_bytes()) {
Ok(()) => (),
Err(_) => {
warn!("cannot send endian byte");