rv32: rm irq & vexriscv-rust

Signed-off-by: occheung <dc@m-labs.hk>

artiq/firmware/libboard_misoc/Cargo.toml

@@ -17,7 +17,6 @@ byteorder = { version = "1.0", default-features = false }
 log = { version = "0.4", default-features = false, optional = true }
 smoltcp = { version = "0.6.0", default-features = false, optional = true }
 riscv = { version = "0.6.0", features = ["inline-asm"] }
-vexriscv = { git = "https://github.com/occheung/vexriscv-rust.git", features = ["inline-asm"] }
 
 [features]
 uart_console = []

artiq/firmware/libboard_misoc/lib.rs

@@ -18,9 +18,6 @@ mod arch;
 #[cfg(target_arch = "riscv32")]
 extern crate riscv;
 
-#[cfg(target_arch = "riscv32")]
-extern crate vexriscv;
-
 pub use arch::*;
 
 include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));

artiq/firmware/libboard_misoc/riscv32imac/irq.rs

@@ -1,46 +0,0 @@
-use core::{convert::TryFrom};
-use riscv::register::mstatus;
-use vexriscv::register::{vmim, vmip};
-
-#[inline]
-pub fn get_ie() -> bool {
-    mstatus::read().mie()
-}
-
-#[inline]
-pub fn set_ie(ie: bool) {
-    unsafe {
-        if ie {
-            mstatus::set_mie()
-        } else {
-            mstatus::clear_mie()
-        }
-    }
-}
-
-#[inline]
-pub fn get_mask() -> u32 {
-    u32::try_from(vmim::read()).unwrap()
-}
-
-#[inline]
-pub fn set_mask(mask: u32) {
-    vmim::write(usize::try_from(mask).unwrap())
-}
-
-#[inline]
-pub fn pending_mask() -> u32 {
-    u32::try_from(vmip::read()).unwrap()
-}
-
-pub fn enable(irq: u32) {
-    set_mask(get_mask() | (1 << irq))
-}
-
-pub fn disable(irq: u32) {
-    set_mask(get_mask() & !(1 << irq))
-}
-
-pub fn is_pending(irq: u32) -> bool {
-    get_mask() & (1 << irq) != 0
-}

artiq/firmware/libboard_misoc/riscv32imac/mod.rs

@@ -1,3 +1,2 @@
-pub mod irq;
 pub mod cache;
 pub mod boot;