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3660 Commits

Author SHA1 Message Date
Robert Jördens 01bfe54dde phaser: actually enable stpl 2016-10-13 14:09:29 +02:00
Robert Jördens 78a41eec8f phaser: kc705: syntax 2016-10-13 12:38:32 +02:00
Florent Kermarrec af0e8582a2 phaser: use new jesd clocking 2016-10-13 11:51:06 +02:00
Robert Jördens 81511feab8 phaser: README: specify versions 2016-10-12 17:13:06 +02:00
Robert Jördens 9c8b21b3f4 phaser: let link settle a bit longer before starting 2016-10-12 16:13:34 +02:00
Robert Jördens 9880b1ebd0 phaser: update README 2016-10-12 16:01:07 +02:00
Robert Jördens 0d1ed247e2 phaser: tweak sawg example 2016-10-12 16:01:07 +02:00
Robert Jördens 2d14864c6d Revert "phaser: 500 MHz dacclock" 
This reverts commit 5f737bef76.
 2016-10-12 16:01:07 +02:00
Florent Kermarrec 12b8598b84 stpl: fix byte ordering 2016-10-12 15:59:27 +02:00
Robert Jördens 9644a3a362 ad9154: mix mode addr, digital gain must be on 2016-10-12 15:00:53 +02:00
Robert Jördens 4376ef5615 phaser: slow down spi a bit 2016-10-12 14:37:43 +02:00
Robert Jördens 3f1d96b68d phaser: tweak dac_setup 2016-10-12 14:22:57 +02:00
Robert Jördens 466d1e8304 phaser: update stpl 2016-10-12 14:22:21 +02:00
Robert Jördens 5f737bef76 phaser: 500 MHz dacclock 2016-10-12 14:03:08 +02:00
Robert Jördens 3b1d5d7eb6 phaser: verify flags in dac_setup 2016-10-12 12:19:08 +02:00
Robert Jördens 1117fe191b phaser: support core stpl 2016-10-12 12:03:29 +02:00
Robert Jördens f515c11f26 phaser: fix refclk period spec 2016-10-11 20:13:34 +02:00
Robert Jördens bae5b73155 phaser: comment out stpl test 2016-10-11 19:50:19 +02:00
Robert Jördens 2b1cca2e7e phaser: stpl 2016-10-11 19:29:27 +02:00
Robert Jördens e4d1f6cf1f README_PHASER: update 2016-10-10 18:49:24 +02:00
Robert Jördens 18d18b6685 phaser: add sync ttl input for monitoring 2016-10-10 17:13:23 +02:00
Robert Jördens f5f7acc1f8 ttl_simple: add pure Input 
(no Tristate for internal signals)
 2016-10-10 17:13:23 +02:00
Robert Jördens e27228fdd5 ad9516: duty cycle correction 2016-10-10 17:13:23 +02:00
Florent Kermarrec c08caae171 phaser: use qpll 2016-10-10 17:05:42 +02:00
Robert Jördens 5f7229ef92 ad9154: tweak jesd prbs test 2016-10-09 20:34:15 +02:00
Robert Jördens 1f93658724 phaser/dac_setup: clear sticky bits, use syncmode=9 2016-10-07 18:54:21 +02:00
Robert Jördens 89a30b6f7c phaser: error on startup kernel 2016-10-08 00:02:38 +08:00
Robert Jördens 4e60a6ac71 phaser: tweak sawg example 2016-10-08 00:02:24 +08:00
Robert Jördens 1157a3a54b ad9514_status: more info 2016-10-07 15:42:46 +02:00
Robert Jördens 72932fccec phaser: fix sysref for 250 MHz sample rate 2016-10-07 15:40:00 +02:00
Robert Jördens cfd2fe8627 phaser: fix fpga deviceclock divider 2016-10-07 13:40:45 +02:00
Robert Jördens 9b860b26e8 phaser: fix rtio pll inputs 2016-10-07 13:00:42 +02:00
Robert Jördens c846e758f1 phaser: fix startup_kernel/ceil 2016-10-07 12:57:38 +02:00
Robert Jördens 09434ec054 phaser: also adapt rtio_crg 2016-10-07 12:44:22 +02:00
Florent Kermarrec e998a980b3 phaser/startup: use get_configuration_checksum() 2016-10-07 09:00:01 +02:00
Florent Kermarrec b02a7234f6 phaser: use 125MHz refclk for jesd 2016-10-07 08:59:34 +02:00
Robert Jördens 4390fea437 phaser status: add statusmode stuff for serdes pll 2016-10-06 17:36:54 +02:00
Robert Jördens 01bc7faacc dac_setup: cleanup, add doc 2016-10-06 17:27:50 +02:00
Robert Jördens fee7831573 phaser: split setup 2016-10-06 16:48:03 +02:00
Robert Jördens 1193ba4bf4 ad9154: merge csr spaces 2016-10-06 16:21:15 +02:00
Robert Jördens 4d87f0e9e0 phaser: instantiate jesd204b core, wire up 2016-10-06 14:44:22 +02:00
Robert Jördens f62d60093e README_PHASER: update 2016-10-06 09:58:05 +02:00
Robert Jördens d13f67cf63 phaser: fix README 2016-10-05 19:26:33 +02:00
Robert Jördens c54b6e2f3c phaser: add README 2016-10-05 19:24:34 +02:00
Robert Jördens 4a0eaf0f95 phaser: add jesd204b rtio dds 
gateware: add jesd204b awg

gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce

sawg: kernel support and docs

sawg: coredevice api fixes

sawg: example ddb/experiment

phaser: add conda package

examples/phaser: typo

sawg: adapt tests, fix accu stb

sawg: tweak dds parameters

sawg: move/adapt/extend tests

sawg: test phy, refactor

phaser: non-rtio spi

phaser: target cli update

phaser: ad9154-fmc-ebz pins

phaser: reorganize fmc signal naming

phaser: add test mode stubs

phaser: txen is LVTTL

phaser: clk spi xfer test

phaser: spi for ad9154 and ad9516

phaser: spi tweaks

ad9154: add register map from ad9144.xml

ad9516: add register map from ad9517.xml and manual adaptation

ad9154_reg: just generate getter/setter macros as well

ad9154: reg WIP

ad9154: check and fix registers

kc705: single ended rtio_external_clk

use single ended user_sma_clk_n instead of p/n to free up one clock sma

kc705: mirror clk200 at user_sma_clock_p

ad9516_regs.h: fix B_COUNTER_MSB

phase: wire up clocking differently

needs patched misoc

kc705: feed rtio_external_clock directly

kc705: remove rtio_external_clk for phaser

phaser: spi tweaks

ad9516: some startup

ad9516_reg fixes

phaser: setup ad9516 for supposed 500 MHz operation

ad9516: use full duplex spi

ad9154_reg: add CONFIG_REG_2

ad9154_reg: fixes

phaser: write some ad9154 config

ad9154_reg: fixes

ad9154: more init, and human readable setup

ad9154/ad9516: merge spi support

ad9154: status readout

Revert "kc705: remove rtio_external_clk for phaser"

This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.

Revert "kc705: feed rtio_external_clock directly"

This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.

Revert "phase: wire up clocking differently"

This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.

Revert "kc705: mirror clk200 at user_sma_clock_p"

This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.

Revert "kc705: single ended rtio_external_clk"

This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.

ad9516: 2000 MHz clock

phaser: test clock dist

phaser: test freqs

ad9154: iostandards

phaser: drop clock monitor

phaser: no separate i2c

phaser: drive rtio from refclk, wire up sysref

phaser: ttl channel for sync

ad9154: 4x interp, status, tweaks

phaser: sync/sysref 33V banks

phaser: sync/sysref LVDS_25 inputs are VCCO tolerant

phaser: user input-only ttls

phaser: rtio fully from refclk

ad9154: reg name usage fix

ad9154: check register modifications

Revert "ad9154: check register modifications"

This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.

ad9154: fix status code

ad9154: addrinc, recal serdes pll

phaser: coredevice, example tweaks

sawg: missing import

sawg: type fixes

ad9514: move setup functions

ad9154: msb first also decreasing addr

phaser: use sys4x for rtio internal ref

phaser: move init code to main

phaser: naming cleanup

phaser: cleanup pins

phaser: move spi to kernel cpu

phaser: kernel support for ad9154 spi

ad9154: add r/w methods

ad9154: need return annotations

ad9154: r/w methods are kernels

ad9154_reg: portable helpers

phaser: cleanup startup kernel

ad9154: status test

ad9154: prbs test

ad9154: move setup, document

phaser: more documentation
 2016-10-05 16:17:50 +02:00
Robert Jördens 2bc5dc4ecb i2c: cleanup includes 2016-10-05 16:17:50 +02:00
Robert Jördens a91ed8394c rtio: add input-only channel 2016-10-05 16:17:50 +02:00
Robert Jördens 279f0d568d rtio: support differential ttl 2016-10-05 16:17:50 +02:00
Robert Jördens fdadf550fb RELEASE_NOTES: 2.0 2016-09-24 18:53:36 +02:00
Sebastien Bourdeauducq 2701b914e2 conda: update migen version requirements 2016-09-24 21:02:19 +08:00