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phaser: fix fpga deviceclock divider

This commit is contained in:
Robert Jördens 2016-10-07 13:40:45 +02:00
parent 9b860b26e8
commit cfd2fe8627
1 changed files with 1 additions and 1 deletions
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2
artiq/examples/phaser/startup_kernel.py
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@ -49,7 +49,7 @@ class StartupKernel(EnvExperiment):
# FPGA deviceclk, dclk/4
self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
self.ad9154.clock_write(AD9516_DIVIDER_0_0,
self.ad9154.clock_write(AD9516_DIVIDER_4_0,
(4//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
(4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)