flake: update dependicies (fix rebase)

Update EMIO to Emio
Re-introduce deleted whitespace
2024-09-30 08:37:50 -07:00 · 2024-09-27 18:55:32 -07:00 · 2024-09-25 19:28:47 -07:00 · 2024-09-24 23:24:50 -07:00 · 2024-09-23 19:46:10 -07:00 · 2024-09-23 13:39:11 -07:00
12 changed files with 93 additions and 104 deletions
--- a/flake.lock
+++ b/flake.lock
@ -1,12 +1,28 @@
 {
  "nodes": {
+    "mozilla-overlay": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1704373101,
+        "narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
+        "owner": "mozilla",
+        "repo": "nixpkgs-mozilla",
+        "rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
+        "type": "github"
+      },
+      "original": {
+        "owner": "mozilla",
+        "repo": "nixpkgs-mozilla",
+        "type": "github"
+      }
+    },
    "nixpkgs": {
      "locked": {
-        "lastModified": 1731652201,
-        "narHash": "sha256-XUO0JKP1hlww0d7mm3kpmIr4hhtR4zicg5Wwes9cPMg=",
+        "lastModified": 1720386169,
+        "narHash": "sha256-NGKVY4PjzwAa4upkGtAMz1npHGoRzWotlSnVlqI40mo=",
        "owner": "NixOS",
        "repo": "nixpkgs",
-        "rev": "c21b77913ea840f8bcf9adf4c41cecc2abffd38d",
+        "rev": "194846768975b7ad2c4988bdb82572c00222c0d7",
        "type": "github"
      },
      "original": {
@ -18,29 +34,8 @@
    },
    "root": {
      "inputs": {
-        "nixpkgs": "nixpkgs",
-        "rust-overlay": "rust-overlay"
-      }
-    },
-    "rust-overlay": {
-      "inputs": {
-        "nixpkgs": [
-          "nixpkgs"
-        ]
-      },
-      "locked": {
-        "lastModified": 1719454714,
-        "narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
-        "owner": "oxalica",
-        "repo": "rust-overlay",
-        "rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
-        "type": "github"
-      },
-      "original": {
-        "owner": "oxalica",
-        "ref": "snapshot/2024-08-01",
-        "repo": "rust-overlay",
-        "type": "github"
+        "mozilla-overlay": "mozilla-overlay",
+        "nixpkgs": "nixpkgs"
      }
    }
  },
--- a/flake.nix
+++ b/flake.nix
@ -2,28 +2,29 @@
  description = "Bare-metal Rust on Zynq-7000";

  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
-  inputs.rust-overlay = {
-    url = "github:oxalica/rust-overlay?ref=snapshot/2024-08-01";
-    inputs.nixpkgs.follows = "nixpkgs";
-  };
+  inputs.mozilla-overlay = { url = github:mozilla/nixpkgs-mozilla; flake = false; };

-  outputs = { self, nixpkgs, rust-overlay }:
+  outputs = { self, nixpkgs, mozilla-overlay }:
    let
-      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import rust-overlay) crosspkgs-overlay ]; };
+      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) crosspkgs-overlay ]; };
      
-      rust = pkgs.rust-bin.nightly."2021-01-28".default.override {
-        extensions = [ "rust-src" ];
-        targets = [ ];
+      rustManifest = pkgs.fetchurl {
+        url = "https://static.rust-lang.org/dist/2021-01-29/channel-rust-nightly.toml";
+        sha256 = "sha256-EZKgw89AH4vxaJpUHmIMzMW/80wAFQlfcxRoBD9nz0c=";
      };
-      rustPlatform = pkgs.makeRustPlatform {
-        rustc = rust // {
-          # https://github.com/oxalica/rust-overlay/commit/c48c2d76b68dd9ede0815fec53479375c61af857
-          targetPlatforms = pkgs.lib.platforms.all;
-          tier1TargetPlatforms = pkgs.lib.platforms.all;
-          badTargetPlatforms = [ ];
+      rustTargets = [];
+      rustChannelOfTargets = _channel: _date: targets:
+        (pkgs.lib.rustLib.fromManifestFile rustManifest {
+          inherit (pkgs) stdenv lib fetchurl patchelf;
+          }).rust.override {
+          inherit targets;
+          extensions = ["rust-src"];
        };
+      rust = rustChannelOfTargets "nightly" null rustTargets;
+      rustPlatform = pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
+        rustc = rust;
        cargo = rust;
-      };
+      });
      
      # https://doc.rust-lang.org/rustc/linker-plugin-lto.html#toolchain-compatibility
      llvmPackages_11 = pkgs.recurseIntoAttrs (pkgs.callPackage (import ./llvm/11) ({
--- a/libboard_zynq/src/ddr/mod.rs
+++ b/libboard_zynq/src/ddr/mod.rs
@ -249,9 +249,9 @@ impl DdrRam {
        #[cfg(feature = "target_ebaz4205")]
        self.regs.dram_param0.write(
            regs::DramParam0::zeroed()
-                .t_rc(0x1a)
-                .t_rfc_min(0x56)
-                .post_selfref_gap_x32(0x10)
+                .t_rc(0x1a) // 48.75 ns / 1.875 ns = 26 clock cycles
+                .t_rfc_min(0x56) // 160 ns / 1.875 ns = 85.333 --> 86 clock cycles
+                .post_selfref_gap_x32(0x10) // Default value
        );
        #[cfg(feature = "target_redpitaya")]
        self.regs.dram_param0.write(
@ -270,8 +270,8 @@ impl DdrRam {
        #[cfg(feature = "target_ebaz4205")]
        self.regs.dram_param1.modify(
            |_, w| w
-                .t_faw(0x16)
-                .t_ras_min(0x13)
+                .t_faw(0x16) // 40 ns / 1.875 ns = 21.33 --> 22 clock cycles
+                .t_ras_min(0x13) // 35 ns / 1.875 ns = 18.66 --> 19 clock cycles
        );
        #[cfg(feature = "target_redpitaya")]
        self.regs.dram_param1.modify(
@ -478,12 +478,11 @@ impl DdrRam {
        let megabytes = 1023;
        #[cfg(any(
            feature = "target_coraz7",
+            feature = "target_ebaz4205",
            feature = "target_redpitaya",
            feature = "target_kasli_soc",
        ))]
        let megabytes = 512;
-        #[cfg(feature = "target_ebaz4205")]
-        let megabytes = 256;

        megabytes * 1024 * 1024
    }
--- a/libboard_zynq/src/eth/phy/mod.rs
+++ b/libboard_zynq/src/eth/phy/mod.rs
@ -83,7 +83,7 @@ pub struct Phy {
 const OUI_MARVELL: u32 = 0x005043;
 const OUI_REALTEK: u32 = 0x000732;
 const OUI_LANTIQ : u32 = 0x355969;
-const OUI_ICPLUS : u32 = 0x0090c3;
+const OUI_ICPLUS : u32 = 0x02430c;

 //only change pages on Kasli-SoC's Marvel 88E11xx
 #[cfg(feature="target_kasli_soc")]
@ -123,6 +123,7 @@ impl Phy {
                    // IP101G-DS-R01
                    model: 5,
                    rev: 4,
+                    ..
                }) => true,
                _ => false,
            }
--- a/libboard_zynq/src/eth/phy/status.rs
+++ b/libboard_zynq/src/eth/phy/status.rs
@ -55,27 +55,7 @@ impl Status {
    pub fn get_link(&self) -> Option<Link> {
        if ! self.link_status() {
            None
-        } else if self.cap_100base_tx_full() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Full,
-            })
-        } else if self.cap_100base_tx_half() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Half,
-            })
-        } else if self.cap_100base_t4() {
-            Some(Link {
-                speed: LinkSpeed::S100,
-                duplex: LinkDuplex::Half,
-            })
-        } else if self.cap_10base_t2_full() {
-            Some(Link {
-                speed: LinkSpeed::S10,
-                duplex: LinkDuplex::Full,
-            })
-        } else if self.cap_10base_t2_half() {
+        } else if self.cap_10base_t_half() {
            Some(Link {
                speed: LinkSpeed::S10,
                duplex: LinkDuplex::Half,
@ -85,11 +65,31 @@ impl Status {
                speed: LinkSpeed::S10,
                duplex: LinkDuplex::Full,
            })
-        } else if self.cap_10base_t_half() {
+        } else if self.cap_10base_t2_half() {
            Some(Link {
                speed: LinkSpeed::S10,
                duplex: LinkDuplex::Half,
            })
+        } else if self.cap_10base_t2_full() {
+            Some(Link {
+                speed: LinkSpeed::S10,
+                duplex: LinkDuplex::Full,
+            })
+        } else if self.cap_100base_t4() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Half,
+            })
+        } else if self.cap_100base_tx_half() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Half,
+            })
+        } else if self.cap_100base_tx_full() {
+            Some(Link {
+                speed: LinkSpeed::S100,
+                duplex: LinkDuplex::Full,
+            })
        } else {
            None
        }
--- a/libboard_zynq/src/i2c/eeprom.rs
+++ b/libboard_zynq/src/i2c/eeprom.rs
@ -4,7 +4,6 @@ use embedded_hal::timer::CountDown;

 pub struct EEPROM<'a> {
    i2c: &'a mut I2c,
-    #[cfg(not(feature = "target_ebaz4205"))]
    port: u8,
    address: u8,
    page_size: u8,
@ -47,11 +46,6 @@ impl<'a> EEPROM<'a> {
        Ok(())
    }

-    #[cfg(feature = "target_ebaz4205")]
-    fn select(&mut self) -> Result<(), &'static str> {
-        Ok(())
-    }
-
    /// Random read
    pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> {
        self.select()?;
--- a/libboard_zynq/src/i2c/mod.rs
+++ b/libboard_zynq/src/i2c/mod.rs
@ -2,13 +2,10 @@

 mod regs;
 pub mod eeprom;
-#[cfg(not(feature = "target_ebaz4205"))]
 use super::slcr;
 use super::time::Microseconds;
 use embedded_hal::timer::CountDown;
-use libregister::{RegisterR, RegisterRW};
-#[cfg(not(feature = "target_ebaz4205"))]
-use libregister::RegisterW;
+use libregister::{RegisterR, RegisterRW, RegisterW};
 #[cfg(feature = "target_kasli_soc")]
 use log::info;

@ -25,10 +22,9 @@ pub struct I2c {
 }

 impl I2c {
-    #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+    #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
    pub fn i2c0() -> Self {
        // Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
-        #[cfg(not(feature = "target_ebaz4205"))]
        slcr::RegisterBlock::unlocked(|slcr| {
            // SCL
            slcr.mio_pin_50.write(
--- a/libboard_zynq/src/i2c/regs.rs
+++ b/libboard_zynq/src/i2c/regs.rs
@ -21,7 +21,6 @@ use libregister::{
 // Current compatibility:
 // zc706: GPIO 50, 51 == SCL, SDA
 // kasli_soc: GPIO 50, 51 == SCL, SDA; GPIO 33 == I2C_SW_RESET
-// ebaz4205: GPIO (EMIO)

 pub struct RegisterBlock {
    pub gpio_output_mask: &'static mut GPIOOutputMask,
@ -49,17 +48,17 @@ register!(gpio_output_mask,
          /// MASK_DATA_1_MSW:
          /// Maskable output data for MIO[53:48]
          GPIOOutputMask, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOOutputMask, 0xE000A00C, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_mask,
              /// Output for SCL
              scl_o, 2);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_mask,
              /// Output for SDA
              sda_o, 3);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bits!(gpio_output_mask,
               /// Mask for keeping bits except SCL and SDA unchanged
               mask, u16, 16, 31);
@ -83,13 +82,13 @@ register!(gpio_input,
          /// DATA_1_RO:
          /// Input data for MIO[53:32]
          GPIOInput, RO, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOInput, 0xE000A064, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_input,
              /// Input for SCL
              scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_input,
              /// Input for SDA
              sda, 19);
@ -99,13 +98,13 @@ register!(gpio_direction,
          /// DIRM_1:
          /// Direction mode for MIO[53:32]; 0/1 = in/out
          GPIODirection, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIODirection, 0xE000A244, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_direction,
              /// Direction for SCL
              scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_direction,
              /// Direction for SDA
              sda, 19);
@ -118,13 +117,13 @@ register!(gpio_output_enable,
          /// OEN_1:
          /// Output enable for MIO[53:32]
          GPIOOutputEnable, RW, u32);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_at!(GPIOOutputEnable, 0xE000A248, new);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_enable,
              /// Output enable for SCL
              scl, 18);
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 register_bit!(gpio_output_enable,
              /// Output enable for SDA
              sda, 19);
--- a/libboard_zynq/src/lib.rs
+++ b/libboard_zynq/src/lib.rs
@ -19,7 +19,7 @@ pub mod gic;
 pub mod time;
 pub mod timer;
 pub mod sdio;
-#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))]
+#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
 pub mod i2c;
 pub mod logger;
 pub mod ps7_init;
--- a/libconfig/src/net_settings.rs
+++ b/libconfig/src/net_settings.rs
@ -55,6 +55,10 @@ pub fn get_addresses(cfg: &Config) -> NetAddresses {
    let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);
    #[cfg(feature = "target_redpitaya")]
    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 55);
+    #[cfg(feature = "target_ebaz4205")]
+    let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x56]);
+    #[cfg(feature = "target_ebaz4205")]
+    let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
    #[cfg(feature = "target_kasli_soc")]
    let mut hardware_addr = get_address_from_eeprom();
    #[cfg(feature = "target_kasli_soc")]
--- a/openocd/ebaz4205.cfg
+++ b/openocd/ebaz4205.cfg
@ -4,7 +4,7 @@ adapter driver ftdi
 ftdi vid_pid 0x0403 0x6010
 ftdi channel 0
 # Every pin set as high impedance except TCK, TDI, TDO and TMS
-ftdi layout_init 0x0088 0x008b
+ftdi layout_init 0x0008 0x000b

 # nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
 # This choice is arbitrary. Use other GPIO pin if desired.
Author	SHA1	Message	Date
newell	7213cfb1f8	flake: update dependicies (fix rebase)	2024-09-30 08:37:50 -07:00
newell	db22dafe28	Update EMIO to Emio	2024-09-27 18:55:32 -07:00
newell	8f2dc94cf8	Re-introduce deleted whitespace	2024-09-25 19:28:47 -07:00
newell	f2eebf44e9	Review update	2024-09-24 23:24:50 -07:00
newell	7453a20420	Add ebaz4205 to build targets	2024-09-23 19:46:10 -07:00
newell	41f780e118	Clean up branch	2024-09-23 13:39:11 -07:00
newell	c3d92abe99	Update eth/mod.rs	2024-09-23 11:25:41 -07:00
newell	6c3d901f00	Create EMIO PLLSource	2024-09-20 15:23:46 -07:00
newell	bb76c13ee0	Remove cfg for eth	2024-09-05 22:31:42 -07:00
newell	eae21579bc	More updates. Fixed openocd.	2024-09-04 16:05:55 -07:00
newell	a75568bd42	EBAZ4205 Initial commit	2024-08-13 14:01:46 -07:00