forked from M-Labs/zynq-rs
Update eth/mod.rs
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@ -298,16 +298,6 @@ impl Eth<Gem0, (), ()> {
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);
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});
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// This didn't help, might not need, keep for now, and remove later to test.
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#[cfg(feature = "target_ebaz4205")]
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slcr::RegisterBlock::unlocked(|slcr| {
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// VREF internal generator
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slcr.gpiob_ctrl.write(
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slcr::GpiobCtrl::zeroed()
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.vref_en(true)
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);
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});
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Self::gem0(macaddr)
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}
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@ -328,12 +318,8 @@ impl Eth<Gem1, (), ()> {
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impl<GEM: Gem> Eth<GEM, (), ()> {
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fn gem_common(macaddr: [u8; 6]) -> Self {
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#[cfg(not(feature = "target_ebaz4205"))]
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GEM::setup_clock(TX_1000);
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#[cfg(feature = "target_ebaz4205")]
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GEM::setup_clock(TX_100);
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#[cfg(feature="target_kasli_soc")]
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{
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let mut eth_reset_pin = PhyRst::rst_pin();
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@ -348,14 +334,6 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
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inner.configure(macaddr);
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// Used for debugging MDIO
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// loop {
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// let _phy = Phy::find(&mut inner);
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// for _ in 0..100_000_000 {
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// asm::nop();
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// }
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// }
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let phy = Phy::find(&mut inner).expect("phy");
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phy.reset(&mut inner);
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phy.restart_autoneg(&mut inner);
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