forked from M-Labs/zynq-rs
Clean up branch
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@ -249,9 +249,9 @@ impl DdrRam {
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#[cfg(feature = "target_ebaz4205")]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1a) // 48.75 ns / 1.875 ns = 26 clock cycles
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.t_rfc_min(0x56) // 160 ns / 1.875 ns = 85.333 --> 86 clock cycles
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.post_selfref_gap_x32(0x10) // Default value
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.t_rc(0x1a)
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.t_rfc_min(0x56)
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.post_selfref_gap_x32(0x10)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param0.write(
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@ -270,8 +270,8 @@ impl DdrRam {
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#[cfg(feature = "target_ebaz4205")]
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self.regs.dram_param1.modify(
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|_, w| w
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.t_faw(0x16) // 40 ns / 1.875 ns = 21.33 --> 22 clock cycles
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.t_ras_min(0x13) // 35 ns / 1.875 ns = 18.66 --> 19 clock cycles
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.t_faw(0x16)
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.t_ras_min(0x13)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param1.modify(
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@ -16,8 +16,6 @@ pub mod tx;
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use super::time::Milliseconds;
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use embedded_hal::timer::CountDown;
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use libcortex_a9::asm;
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/// Size of all the buffers
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pub const MTU: usize = 1536;
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/// Maximum MDC clock
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@ -84,7 +84,6 @@ const OUI_MARVELL: u32 = 0x005043;
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const OUI_REALTEK: u32 = 0x000732;
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const OUI_LANTIQ : u32 = 0x355969;
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const OUI_ICPLUS : u32 = 0x0090c3;
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// const OUI_ICPLUS : u32 = 0x02430c;
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//only change pages on Kasli-SoC's Marvel 88E11xx
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#[cfg(feature="target_kasli_soc")]
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@ -12,7 +12,7 @@ pub enum PllSource {
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IoPll = 0b000,
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ArmPll = 0b010,
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DdrPll = 0b011,
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// Ethernet controller via EMIO
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// Ethernet controller 0 EMIO clock
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EMIO = 0b100,
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}
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