Clean up branch

libboard_zynq/src/ddr/mod.rs

@@ -249,9 +249,9 @@ impl DdrRam {
         #[cfg(feature = "target_ebaz4205")]
         self.regs.dram_param0.write(
             regs::DramParam0::zeroed()
-                .t_rc(0x1a) // 48.75 ns / 1.875 ns = 26 clock cycles
-                .t_rfc_min(0x56) // 160 ns / 1.875 ns = 85.333 --> 86 clock cycles
-                .post_selfref_gap_x32(0x10) // Default value
+                .t_rc(0x1a)
+                .t_rfc_min(0x56)
+                .post_selfref_gap_x32(0x10)
         );
         #[cfg(feature = "target_redpitaya")]
         self.regs.dram_param0.write(
@@ -270,8 +270,8 @@ impl DdrRam {
         #[cfg(feature = "target_ebaz4205")]
         self.regs.dram_param1.modify(
             |_, w| w
-                .t_faw(0x16) // 40 ns / 1.875 ns = 21.33 --> 22 clock cycles
-                .t_ras_min(0x13) // 35 ns / 1.875 ns = 18.66 --> 19 clock cycles
+                .t_faw(0x16)
+                .t_ras_min(0x13)
         );
         #[cfg(feature = "target_redpitaya")]
         self.regs.dram_param1.modify(

libboard_zynq/src/eth/mod.rs

@@ -16,8 +16,6 @@ pub mod tx;
 use super::time::Milliseconds;
 use embedded_hal::timer::CountDown;
 
-use libcortex_a9::asm;
-
 /// Size of all the buffers
 pub const MTU: usize = 1536;
 /// Maximum MDC clock

libboard_zynq/src/eth/phy/mod.rs

@@ -84,7 +84,6 @@ const OUI_MARVELL: u32 = 0x005043;
 const OUI_REALTEK: u32 = 0x000732;
 const OUI_LANTIQ : u32 = 0x355969;
 const OUI_ICPLUS : u32 = 0x0090c3;
-// const OUI_ICPLUS : u32 = 0x02430c;
 
 //only change pages on Kasli-SoC's Marvel 88E11xx
 #[cfg(feature="target_kasli_soc")]

libboard_zynq/src/slcr.rs

@@ -12,7 +12,7 @@ pub enum PllSource {
     IoPll  = 0b000,
     ArmPll = 0b010,
     DdrPll = 0b011,
-    // Ethernet controller via EMIO
+    // Ethernet controller 0 EMIO clock
     EMIO   = 0b100,
 }