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zynq-rs/src/main.rs

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#![no_std]
#![no_main]
#![feature(asm)]
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#![feature(global_asm)]
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#![feature(naked_functions)]
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use core::fmt::Write;
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use r0::zero_bss;
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mod regs;
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mod cortex_a9;
mod slcr;
mod uart;
use uart::Uart;
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mod eth;
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use crate::cortex_a9::{asm, regs::*};
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extern "C" {
static mut __bss_start: u32;
static mut __bss_end: u32;
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static mut __stack_start: u32;
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}
#[link_section = ".text.boot"]
#[no_mangle]
#[naked]
pub unsafe extern "C" fn _boot_cores() -> ! {
const CORE_MASK: u32 = 0x3;
match MPIDR.get() & CORE_MASK {
0 => {
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SP.set(&mut __stack_start as *mut _ as u32);
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boot_core0();
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}
_ => loop {
// if not core0, infinitely wait for events
asm::wfe();
},
}
}
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#[naked]
#[inline(never)]
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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zero_bss(&mut __bss_start, &mut __bss_end);
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main();
panic!("return from main");
}
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fn l1_cache_init() {
// Invalidate TLBs
tlbiall();
// Invalidate I-Cache
iciallu();
// Invalidate Branch Predictor Array
bpiall();
// Invalidate D-Cache
dccisw();
// (Initialize MMU)
// Enable I-Cache and D-Cache
sctlr();
// Synchronization barriers
// Allows MMU to start
asm::dsb();
// Flushes pre-fetch buffer
asm::isb();
}
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const UART_RATE: u32 = 115_200;
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fn main() {
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let mut uart = Uart::serial(UART_RATE);
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writeln!(uart, "\r\nHello World!\r");
let mut eth = eth::Eth::default();
writeln!(uart, "Eth on\r");
use eth::phy::PhyAccess;
for addr in 1..=31 {
let detect = eth.read_phy(addr, 1);
let id1 = eth.read_phy(addr, 2);
let id2 = eth.read_phy(addr, 3);
writeln!(uart, "phy {}: {:04X} {:04X} {:04X}\r", addr, detect, id1, id2);
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}
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while !uart.tx_fifo_empty() {}
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loop {}
panic!("End");
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}
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#[panic_handler]
fn panic(info: &core::panic::PanicInfo) -> ! {
let mut uart = Uart::serial(UART_RATE);
writeln!(uart, "\r\nPanic: {}\r", info);
while !uart.tx_fifo_empty() {}
slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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loop {}
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}
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#[no_mangle]
pub unsafe extern "C" fn PrefetchAbort() {
panic!("PrefetchAbort");
}
#[no_mangle]
pub unsafe extern "C" fn DataAbort() {
panic!("DataAbort");
}