forked from M-Labs/zynq-rs
use uart1 with more configuration
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5d02fe5c95
commit
47ec0116a9
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@ -50,8 +50,11 @@ unsafe fn boot_core0() -> ! {
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}
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fn main() {
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let mut uart = Uart::uart0();
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let mut uart = Uart::uart1();
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writeln!(uart, "Hello World\r").unwrap();
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for i in 0.. {
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writeln!(uart, "i={}\r", i).unwrap();
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}
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let eth = eth::Eth::gem0();
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loop {
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11
src/slcr.rs
11
src/slcr.rs
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@ -75,6 +75,17 @@ impl UartClkCtrl {
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.clkact0(true)
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})
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}
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pub fn enable_uart1(&self) {
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self.modify(|_, w| {
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.clkact1(true)
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})
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}
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}
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register!(uart_rst_ctrl, UartRstCtrl, RW, u32);
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@ -1,6 +1,7 @@
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#![allow(unused)]
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use core::fmt;
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use volatile_register::RW;
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use crate::regs::*;
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@ -19,16 +20,28 @@ pub struct Uart {
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}
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impl Uart {
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pub fn uart0() -> Self {
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let uart_rst_ctrl = super::slcr::UartRstCtrl::new();
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uart_rst_ctrl.reset_uart0();
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// TODO: Route UART 0 RxD/TxD Signals to MIO Pins
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pub fn uart1() -> Self {
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super::slcr::with_slcr(|| {
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let uart_rst_ctrl = super::slcr::UartRstCtrl::new();
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uart_rst_ctrl.reset_uart1();
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let uart_clk_ctrl = super::slcr::UartClkCtrl::new();
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uart_clk_ctrl.enable_uart0();
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// Route UART 1 RxD/TxD Signals to MIO Pins
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unsafe {
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// TX pin
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let mio_pin_48 = &*(0xF80007C0 as *const RW<u32>);
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mio_pin_48.write(0x0000_12E0);
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// RX pin
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let mio_pin_49 = &*(0xF80007C4 as *const RW<u32>);
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mio_pin_49.write(0x0000_12E1);
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}
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let aper_clk_ctrl = super::slcr::AperClkCtrl::new();
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aper_clk_ctrl.enable_uart1();
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let uart_clk_ctrl = super::slcr::UartClkCtrl::new();
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uart_clk_ctrl.enable_uart1();
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});
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let self_ = Uart {
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regs: regs::RegisterBlock::uart0(),
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regs: regs::RegisterBlock::uart1(),
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};
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self_.configure();
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self_
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@ -54,20 +67,25 @@ impl Uart {
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self.regs.mode.write(
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regs::Mode::zeroed()
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.par(parity_mode as u8)
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.chmode(regs::ChannelMode::AutomaticEcho as u8)
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);
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// Configure the Baud Rate
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self.disable_rx();
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self.disable_tx();
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// 9,600 baud
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self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(651));
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self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(7));
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// 115,200 baud
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self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(0x28B));
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self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(0xF));
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// Enable controller
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self.reset_rx();
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self.reset_tx();
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self.enable_rx();
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self.enable_tx();
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self.set_rx_timeout(false);
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self.set_break(false, true);
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}
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fn disable_rx(&self) {
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@ -110,6 +128,20 @@ impl Uart {
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})
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}
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fn set_break(&self, startbrk: bool, stopbrk: bool) {
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self.regs.control.modify(|_, w| {
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w.sttbrk(startbrk)
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.stpbrk(stopbrk)
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})
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}
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// 0 disables
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fn set_rx_timeout(&self, enable: bool) {
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self.regs.control.modify(|_, w| {
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w.rstto(enable)
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})
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}
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pub fn tx_fifo_full(&self) -> bool {
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self.regs.channel_sts.read().txfull()
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}
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@ -2,6 +2,13 @@ use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_at, regs::*};
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pub enum ChannelMode {
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Normal = 0b00,
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AutomaticEcho = 0b01,
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LocalLoopback = 0b10,
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RemoteLoopback = 0b11,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub control: Control,
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@ -33,8 +40,13 @@ register_bit!(control, rxen, 2);
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register_bit!(control, rxdis, 3);
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register_bit!(control, txen, 4);
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register_bit!(control, txdis, 5);
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register_bit!(control, rstto, 6);
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register_bit!(control, sttbrk, 7);
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register_bit!(control, stpbrk, 8);
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register!(mode, Mode, RW, u32);
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/// Channel mode: Defines the mode of operation of the UART.
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register_bits!(mode, chmode, u8, 8, 9);
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register_bits!(mode, par, u8, 3, 5);
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register!(baud_rate_gen, BaudRateGen, RW, u32);
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