forked from M-Labs/zynq-rs
1
0
Fork 0
zynq-rs/src/main.rs

108 lines
1.9 KiB
Rust
Raw Normal View History

2019-05-05 20:56:23 +08:00
#![no_std]
#![no_main]
#![feature(asm)]
2019-05-31 02:30:19 +08:00
#![feature(global_asm)]
2019-05-05 20:56:23 +08:00
#![feature(naked_functions)]
2019-05-07 22:45:31 +08:00
use core::fmt::Write;
2019-05-05 20:56:23 +08:00
use r0::zero_bss;
2019-05-07 05:56:53 +08:00
mod regs;
2019-05-05 20:56:23 +08:00
mod cortex_a9;
mod slcr;
mod uart;
use uart::Uart;
2019-05-08 01:28:33 +08:00
mod eth;
2019-05-05 20:56:23 +08:00
2019-05-24 01:05:06 +08:00
use crate::cortex_a9::{asm, regs::*};
2019-05-05 20:56:23 +08:00
extern "C" {
static mut __bss_start: u32;
static mut __bss_end: u32;
2019-05-27 07:44:24 +08:00
static mut __stack_start: u32;
2019-05-05 20:56:23 +08:00
}
#[link_section = ".text.boot"]
#[no_mangle]
#[naked]
pub unsafe extern "C" fn _boot_cores() -> ! {
const CORE_MASK: u32 = 0x3;
match MPIDR.get() & CORE_MASK {
0 => {
2019-05-27 07:44:24 +08:00
SP.set(&mut __stack_start as *mut _ as u32);
2019-05-20 07:21:22 +08:00
boot_core0();
2019-05-05 20:56:23 +08:00
}
_ => loop {
// if not core0, infinitely wait for events
asm::wfe();
},
}
}
2019-05-30 08:41:44 +08:00
#[naked]
#[inline(never)]
2019-05-20 07:21:22 +08:00
unsafe fn boot_core0() -> ! {
2019-05-24 01:05:06 +08:00
l1_cache_init();
2019-05-20 07:21:22 +08:00
zero_bss(&mut __bss_start, &mut __bss_end);
2019-05-30 08:41:44 +08:00
2019-05-20 07:21:22 +08:00
main();
panic!("return from main");
}
2019-05-24 01:05:06 +08:00
fn l1_cache_init() {
// Invalidate TLBs
tlbiall();
// Invalidate I-Cache
iciallu();
// Invalidate Branch Predictor Array
bpiall();
// Invalidate D-Cache
dccisw();
// (Initialize MMU)
// Enable I-Cache and D-Cache
sctlr();
// Synchronization barriers
// Allows MMU to start
asm::dsb();
// Flushes pre-fetch buffer
asm::isb();
}
2019-05-05 20:56:23 +08:00
fn main() {
2019-05-25 08:38:05 +08:00
let mut uart = Uart::serial(115_200);
loop {
for i in 0.. {
writeln!(uart, "i={}\r", i);
}
2019-05-21 07:30:54 +08:00
}
2019-05-08 01:28:33 +08:00
2019-05-25 09:06:39 +08:00
let eth = eth::Eth::default();
2019-05-08 01:28:33 +08:00
loop {
}
2019-05-05 20:56:23 +08:00
}
2019-05-28 06:28:35 +08:00
#[panic_handler]
fn panic(info: &core::panic::PanicInfo) -> ! {
let mut uart = Uart::serial(UART_RATE);
writeln!(uart, "\r\nPanic: {}\r", info);
while !uart.tx_fifo_empty() {}
slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
unreachable!()
}
2019-05-31 02:30:19 +08:00
#[no_mangle]
pub unsafe extern "C" fn PrefetchAbort() {
panic!("PrefetchAbort");
}
#[no_mangle]
pub unsafe extern "C" fn DataAbort() {
panic!("DataAbort");
}