forked from M-Labs/zynq-rs
1
0
Fork 0
zynq-rs/src/main.rs

63 lines
1.1 KiB
Rust
Raw Normal View History

2019-05-05 20:56:23 +08:00
#![no_std]
#![no_main]
#![feature(asm)]
//[feature(global_asm)]
#![feature(naked_functions)]
2019-05-07 22:45:31 +08:00
use core::fmt::Write;
2019-05-05 20:56:23 +08:00
use panic_abort as _;
use r0::zero_bss;
2019-05-07 05:56:53 +08:00
mod regs;
2019-05-05 20:56:23 +08:00
mod cortex_a9;
mod slcr;
mod uart;
use uart::Uart;
2019-05-08 01:28:33 +08:00
mod eth;
2019-05-05 20:56:23 +08:00
extern "C" {
static mut __bss_start: u32;
static mut __bss_end: u32;
static mut __end: u32;
}
#[link_section = ".text.boot"]
#[no_mangle]
#[naked]
pub unsafe extern "C" fn _boot_cores() -> ! {
use cortex_a9::{asm, regs::*};
const CORE_MASK: u32 = 0x3;
2019-05-20 07:21:22 +08:00
let stack_start = __end + 4096;
2019-05-05 20:56:23 +08:00
match MPIDR.get() & CORE_MASK {
0 => {
2019-05-20 07:21:22 +08:00
SP.set(stack_start);
boot_core0();
2019-05-05 20:56:23 +08:00
}
_ => loop {
// if not core0, infinitely wait for events
asm::wfe();
},
}
}
2019-05-20 07:21:22 +08:00
unsafe fn boot_core0() -> ! {
zero_bss(&mut __bss_start, &mut __bss_end);
main();
panic!("return from main");
}
2019-05-05 20:56:23 +08:00
fn main() {
2019-05-21 07:30:54 +08:00
let mut uart = Uart::uart1();
2019-05-07 22:45:31 +08:00
writeln!(uart, "Hello World\r").unwrap();
2019-05-21 07:30:54 +08:00
for i in 0.. {
writeln!(uart, "i={}\r", i).unwrap();
}
2019-05-08 01:28:33 +08:00
let eth = eth::Eth::gem0();
loop {
}
2019-05-05 20:56:23 +08:00
}