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8918952b96
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complex: lint
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2021-02-12 12:06:00 +01:00 |
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71c6e52f4d
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complex: add some traits
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2021-02-12 12:03:53 +01:00 |
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a6d4099ed3
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lowpass: expose natural gain, add bias
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2021-02-12 11:06:59 +01:00 |
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67f052c0c9
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lockin: add rounding bias
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2021-02-12 11:05:50 +01:00 |
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32b7058b47
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lockin: 2nd order lowpass
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2021-02-11 23:15:32 +01:00 |
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b49f0a2eb9
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complex: log2, update bins
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2021-02-11 18:14:28 +01:00 |
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3ae0b710bc
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lowpass: reimplement better
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2021-02-11 14:30:05 +01:00 |
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a144c099b2
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lowpass: fmt
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2021-02-10 14:10:28 +01:00 |
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beeb43bf8b
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lowpass: robustify
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2021-02-10 13:44:10 +01:00 |
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8d68504026
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lowpass: symmetric code
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2021-02-10 13:31:41 +01:00 |
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13b47556fd
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lowpass: clippy
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2021-02-10 13:27:56 +01:00 |
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30c2c2aac2
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lowpass: i32, no multiplies
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2021-02-10 11:39:19 +01:00 |
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208ba8379a
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dsp, lockin: use cascaded 1st order lowpasses
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2021-02-09 20:37:46 +01:00 |
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31781a9d0e
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iir_int: rounding bias
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2021-02-09 12:17:48 +01:00 |
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473bdaa9bc
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iir_int: use f64 for extreme filters
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2021-02-04 15:21:05 +01:00 |
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f250e036ca
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rpll: simplify parameters, add one test
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2021-02-04 12:46:33 +01:00 |
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dcc71d5d11
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iir: tweak math a bit
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2021-02-02 15:41:47 +01:00 |
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f02d3cc95b
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dsp: clippy
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2021-02-01 18:46:21 +01:00 |
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2a84e3f299
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dsp: remove unused code, let the compiler decide about inlining
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2021-02-01 18:37:05 +01:00 |
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5d7266abbc
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dsp: clippy
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2021-02-01 18:24:51 +01:00 |
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b6e22b576b
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iir: add const fn new()
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2021-02-01 17:18:10 +01:00 |
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ab7e3d229b
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rpll: clean up asserts
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2021-02-01 16:01:05 +01:00 |
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65a3f839a0
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lockin: remove feed()
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2021-02-01 13:42:38 +01:00 |
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90bd4741cc
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dsp/benches: iir vec5
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2021-02-01 13:27:49 +01:00 |
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965c6335e1
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dsp: fmt
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2021-02-01 12:40:12 +01:00 |
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7748d8eb54
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dsp: constructor style
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2021-02-01 12:37:44 +01:00 |
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2c60103696
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dsp: accu: add, iir: rename IIRState to Vec5
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2021-02-01 12:23:47 +01:00 |
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0fd4b167b4
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complex/cossin: decouple modules
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2021-02-01 12:07:03 +01:00 |
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2d43b8970b
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lockin: cleanup
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2021-01-31 20:49:14 +01:00 |
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47089c267c
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dsp: align iir and iir_int, add iir micro benches
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2021-01-31 19:12:24 +01:00 |
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8408bc5811
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dsp/bench: add pll/rpll micro benches
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2021-01-31 18:54:09 +01:00 |
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43342cef91
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rpll: docs
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2021-01-31 18:21:47 +01:00 |
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d281783f2e
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rpll: reduce code
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2021-01-31 18:10:13 +01:00 |
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82c8fa1a07
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rpll: extend tests
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2021-01-31 17:10:03 +01:00 |
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ab20d67a07
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rpll: remove redundant time tracking
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2021-01-31 13:42:15 +01:00 |
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6b2d8169f0
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rpll: more/cleaner tests
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2021-01-31 13:25:01 +01:00 |
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be7aad1b81
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rpll: add unittest
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2021-01-30 20:49:31 +01:00 |
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0d1b237202
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complex: richer API
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2021-01-30 18:05:54 +01:00 |
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36288225b3
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rpll: extend to above-nyquist frequencies
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2021-01-28 22:21:42 +01:00 |
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1749d48ca3
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Revert "rpll: auto-align counter"
This reverts commit dbacc5293e12f712fef7bd85848e1b0bd8fde823.
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2021-01-27 09:01:07 +01:00 |
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45e7d6de3c
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rpll: auto-align counter
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2021-01-27 09:01:07 +01:00 |
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7c1fa9695a
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iir lowpass: f32 is sufficient
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2021-01-26 19:37:05 +01:00 |
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73c98c947a
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iir_int: remove spurious note
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2021-01-26 19:23:23 +01:00 |
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2b439a0231
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lockin: remove broken tests, to be rewritten
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2021-01-26 19:22:02 +01:00 |
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d1f41b3ad5
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int_iir: use taylor for lowpass
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2021-01-26 19:19:09 +01:00 |
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7b9fc3b2b3
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iir_int: move lowpass coefficient calculation to iirstate
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2021-01-26 18:51:20 +01:00 |
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9b3a47e08b
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rpll: refine, simplify, document and comment
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2021-01-26 18:49:31 +01:00 |
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ea7b08fc64
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rpll: refine
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2021-01-26 14:40:44 +01:00 |
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16009c3b7e
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rpll: update lockin integration test
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2021-01-25 12:00:47 +01:00 |
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9f9744b9e6
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rpll: implement
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2021-01-25 11:45:59 +01:00 |
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