pounder_test/src/pounder/dds_output.rs

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use super::QspiInterface;
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use crate::hrtimer::HighResTimerE;
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use ad9959::{Channel, DdsConfig, ProfileSerializer};
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use stm32h7xx_hal as hal;
pub struct DdsOutput {
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_qspi: QspiInterface,
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io_update_trigger: HighResTimerE,
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config: DdsConfig,
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}
impl DdsOutput {
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pub fn new(
_qspi: QspiInterface,
io_update_trigger: HighResTimerE,
dds_config: DdsConfig,
) -> Self {
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Self {
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config: dds_config,
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_qspi,
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io_update_trigger,
}
}
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pub fn builder(&mut self) -> ProfileBuilder {
let builder = self.config.builder();
ProfileBuilder {
dds_stream: self,
serializer: builder,
}
}
fn write_profile(&mut self, profile: &[u32]) {
assert!(profile.len() <= 16);
// Note(unsafe): We own the QSPI interface, so it is safe to access the registers in a raw
// fashion.
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let regs = unsafe { &*hal::stm32::QUADSPI::ptr() };
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for word in profile.iter() {
// Note(unsafe): We are writing to the SPI TX FIFO in a raw manner for performance. This
// is safe because we know the data register is a valid address to write to.
unsafe {
core::ptr::write_volatile(
&regs.dr as *const _ as *mut u32,
*word,
);
}
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}
// Trigger the IO_update signal generating timer to asynchronous create the IO_Update pulse.
self.io_update_trigger.trigger();
}
}
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pub struct ProfileBuilder<'a> {
dds_stream: &'a mut DdsOutput,
serializer: ProfileSerializer,
}
impl<'a> ProfileBuilder<'a> {
pub fn update_channels(
mut self,
channels: &[Channel],
ftw: Option<u32>,
pow: Option<u16>,
acr: Option<u16>,
) -> Self {
self.serializer.update_channels(channels, ftw, pow, acr);
self
}
pub fn write_profile(mut self) {
let profile = self.serializer.finalize();
self.dds_stream.write_profile(profile);
}
}