2020-11-17 21:23:56 +08:00
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use super::QspiInterface;
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2020-11-17 17:51:31 +08:00
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use crate::hrtimer::HighResTimerE;
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use stm32h7xx_hal as hal;
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pub struct DdsOutput {
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2020-11-17 21:23:56 +08:00
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_qspi: QspiInterface,
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2020-11-17 17:51:31 +08:00
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io_update_trigger: HighResTimerE,
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}
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impl DdsOutput {
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2020-11-17 21:23:56 +08:00
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pub fn new(_qspi: QspiInterface, io_update_trigger: HighResTimerE) -> Self {
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2020-11-17 17:51:31 +08:00
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Self {
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2020-11-17 21:23:56 +08:00
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_qspi,
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2020-11-17 17:51:31 +08:00
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io_update_trigger,
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}
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}
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2020-11-17 21:23:56 +08:00
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pub fn write_profile(&mut self, profile: [u32; 4]) {
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2020-11-17 17:51:31 +08:00
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let regs = unsafe { &*hal::stm32::QUADSPI::ptr() };
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unsafe {
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[0],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[1],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[2],
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);
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core::ptr::write_volatile(
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®s.dr as *const _ as *mut u32,
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profile[3],
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);
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}
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// Trigger the IO_update signal generating timer to asynchronous create the IO_Update pulse.
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self.io_update_trigger.trigger();
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}
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}
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