Astro
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b346ea8297
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zynq::flash: fix INST_RDCR
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2019-12-12 00:11:42 +01:00 |
Astro
|
e9b80eaef9
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zynq::flash: don't send excess data, fixes, refactorings
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2019-12-10 02:50:44 +01:00 |
Astro
|
0823a74164
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zynq::flash: fix rx_thres register
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2019-12-10 02:46:25 +01:00 |
Astro
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aab82f6843
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zynq::flash: enable big endian mode
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2019-12-10 02:45:05 +01:00 |
Astro
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f3676c945a
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zynq::flash: flush after instruction
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2019-12-07 02:48:55 +01:00 |
Astro
|
1e465250f5
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zynq::flash: enable/disable spi for every transfer
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2019-12-07 02:11:50 +01:00 |
Astro
|
e37659e4b3
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zynq::flash: refactor
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2019-12-05 01:18:52 +01:00 |
Astro
|
45cc271735
|
zynq::flash: fix + refactor
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2019-12-05 00:05:34 +01:00 |
Astro
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cfaa1213e2
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zynq::flash: add more initialization
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2019-12-03 02:41:49 +01:00 |
Astro
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7107244a6e
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zynq::flash: start implementing Manual mode
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2019-11-30 02:48:39 +01:00 |
Astro
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dd3ad3be67
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zynq::flash: implement stopping LinearAddressing mode
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2019-11-29 23:48:08 +01:00 |
Astro
|
a8a7f11990
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zynq::flash: configure quad i/o fast read mode
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2019-11-29 23:37:54 +01:00 |
Astro
|
78caca1f04
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zynq::flash: setup additional signals
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2019-11-28 03:22:26 +01:00 |
Astro
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5642feb824
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zynq::flash: add missing config bits to enable addressing mode
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2019-11-28 03:02:51 +01:00 |
Astro
|
a199a5dc7d
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zynq::flash: add more setup
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2019-11-23 01:59:24 +01:00 |
Astro
|
3180f1c3f7
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zynq::flash: begin driver implementation
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2019-11-21 00:14:09 +01:00 |
Astro
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8037042040
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zynq::slcr: implement boot_mode bits
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2019-11-20 21:31:54 +01:00 |
Astro
|
6ffcf7d4a4
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ram: lock for concurrent use
this may be reverted if ram allocation shall be more separate.
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2019-11-20 17:25:54 +01:00 |
Astro
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4f8a76e29b
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stdio: lock for use by core1
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2019-11-20 17:00:57 +01:00 |
Astro
|
ff41f4dd2d
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cortex_a9::mutex: restore and fix powersaving behaviour, doc
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2019-11-20 16:30:56 +01:00 |
Astro
|
d89f594ba4
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cortex_a9::mutex: use AtomU32, remove powersaving behavior
Mutex works properly now.
|
2019-11-18 02:37:59 +01:00 |
Astro
|
4e4ff512d9
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add cortex_a9::mutex
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2019-11-18 02:13:54 +01:00 |
Astro
|
85f29ace6b
|
boot: flush cache-line
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2019-11-18 01:22:57 +01:00 |
Astro
|
ef6d0ff3f1
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boot: reset core1 before start
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2019-11-18 00:38:03 +01:00 |
Astro
|
0bc941d789
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main: start_core1
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2019-11-16 00:53:30 +01:00 |
Astro
|
a416f48af1
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main: add empty main_core1()
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2019-11-16 00:21:57 +01:00 |
Astro
|
b6596d930d
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boot: ACTLR.enable_smp()
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2019-11-16 00:12:58 +01:00 |
Astro
|
49901d1b8a
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boot: prepare core1 bootup
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2019-11-15 23:59:01 +01:00 |
Björn Stein
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4a1d0fc0c3
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zynq::mpcore: add register definitions
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2019-11-14 02:11:58 +01:00 |
Astro
|
50481b3a80
|
main: rm obsolete compile feature
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2019-11-13 23:33:11 +01:00 |
Astro
|
b76dc4037d
|
main: change IP address to 192.168.1.51/24
|
2019-11-13 16:02:56 +01:00 |
Astro
|
caa69fda2e
|
main: refactor into boot
|
2019-11-11 02:46:18 +01:00 |
Astro
|
3279aab961
|
main: refactor into abort, panic, ram
|
2019-11-11 02:46:18 +01:00 |
Astro
|
92c274348f
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zynq::eth: enable checksum offload
|
2019-11-11 01:42:41 +01:00 |
Astro
|
3eb7fce572
|
delint
|
2019-11-11 01:42:38 +01:00 |
Astro
|
b1472096ba
|
main: change IP address to 192.168.1.28/24
|
2019-11-11 01:40:07 +01:00 |
Astro
|
cb1b5776cd
|
Cargo.lock: update dependencies
|
2019-11-11 00:45:59 +01:00 |
Astro
|
3496755406
|
update rust + smoltcp
|
2019-11-11 00:28:46 +01:00 |
Astro
|
959bf8a245
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zynq::eth: don't check_link_change if link already established
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2019-11-11 00:08:48 +01:00 |
Astro
|
4d3b2ac7e5
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zynq::ddr: use different data_bus_width for targets
DDR still works only on the zc706, not on the cora z7-10.
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2019-11-11 00:06:35 +01:00 |
Astro
|
cae02947bc
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zynq::eth: remove all memory barriers
They were not the solution.
|
2019-11-10 23:52:55 +01:00 |
Astro
|
afd96bd887
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zynq::clocks: unlock slcr in enable_io()
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2019-11-07 00:13:50 +01:00 |
Astro
|
261455877d
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zynq::ddr: fix DDR 3x/2x setup, print clocks
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2019-11-07 00:13:50 +01:00 |
Astro
|
ff96bf903b
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zynq::ddr: only enable_ddr if no clock yet
that's only an issue for the cora z7
|
2019-11-07 00:13:50 +01:00 |
Astro
|
d2df5652d0
|
Revert "zynq: replace unnecessary slcr::unlocked with new"
This reverts commit 6bee1f44f4 .
|
2019-11-07 00:13:50 +01:00 |
Astro
|
eb56dda44f
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zynq::slcr::unlocked: fix comment
|
2019-11-07 00:13:50 +01:00 |
Sebastien Bourdeauducq
|
6e50b32e80
|
openocd: configure SRST for digilent_jtag_smt2_nc + Zynq
Digilent docs say Zynq boards should connect it to GPIO2.
Closes #2
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2019-11-05 12:36:07 +08:00 |
Astro
|
74c43b3477
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zynq::eth::tx: clear entry.word1 for each packet
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2019-11-04 02:31:40 +01:00 |
Astro
|
99a00e019b
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zynq::eth: implement phy::extended_status, set clock for link speed
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2019-11-04 02:30:00 +01:00 |
Astro
|
961e2e1dd0
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zynq::{ddr, eth}: fix clock divisor calculation
off-by-one, didn't change behavior.
|
2019-11-03 02:23:16 +01:00 |