harry/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Issues Pull Requests Releases Wiki Activity

zynq::flash: add more initialization

Browse Source
This commit is contained in:
Astro 2019-12-03 02:41:49 +01:00
parent 7107244a6e
commit cfaa1213e2
2 changed files with 46 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
src/zynq/flash/mod.rs
View File

@ -160,6 +160,9 @@ impl Flash<()> {
}
fn configure(&mut self, divider: u32) {
self.disable_interrupts();
self.clear_rx_fifo();
// for a baud_rate_div=1 LPBK_DLY_ADJ would be required
let mut baud_rate_div = 2u32;
while baud_rate_div < 7 && 2u32.pow(1 + baud_rate_div) < divider {
@ -170,8 +173,33 @@ impl Flash<()> {
.baud_rate_div(baud_rate_div as u8)
.mode_sel(true)
.leg_flsh(true)
// 32 bits TX FIFO width
.fifo_width(0b11)
);
// Initialize RX/TX pipes thresholds
unsafe {
self.regs.rx_thres.write(32);
self.regs.tx_thres.write(1);
}
}
fn disable_interrupts(&mut self) {
self.regs.intr_dis.write(
regs::IntrDis::zeroed()
.rx_overflow(true)
.tx_fifo_not_full(true)
.tx_fifo_full(true)
.rx_fifo_not_empty(true)
.rx_fifo_full(true)
.tx_fifo_underflow(true)
);
}
fn clear_rx_fifo(&self) {
while self.regs.intr_status.read().rx_fifo_not_empty() {
let _ = self.regs.rx_data.read();
}
}
pub fn linear_addressing_mode(self) -> Flash<LinearAddressing> {

20
src/zynq/flash/regs.rs
View File

@ -6,8 +6,8 @@ use crate::{register, register_bit, register_bits};
pub struct RegisterBlock {
pub config: Config,
pub intr_status: IntrStatus,
pub intr_en: RW<u32>,
pub intr_dis: RW<u32>,
pub intr_en: IntrEn,
pub intr_dis: IntrDis,
pub intr_mask: RO<u32>,
pub enable: Enable,
pub delay: RW<u32>,
@ -85,6 +85,22 @@ register_bit!(intr_status, rx_fifo_not_empty, 4);
register_bit!(intr_status, rx_fifo_full, 5);
register_bit!(intr_status, tx_fifo_underflow, 6);
register!(intr_en, IntrEn, WO, u32);
register_bit!(intr_en, rx_overflow, 0);
register_bit!(intr_en, tx_fifo_not_full, 2);
register_bit!(intr_en, tx_fifo_full, 3);
register_bit!(intr_en, rx_fifo_not_empty, 4);
register_bit!(intr_en, rx_fifo_full, 5);
register_bit!(intr_en, tx_fifo_underflow, 6);
register!(intr_dis, IntrDis, WO, u32);
register_bit!(intr_dis, rx_overflow, 0);
register_bit!(intr_dis, tx_fifo_not_full, 2);
register_bit!(intr_dis, tx_fifo_full, 3);
register_bit!(intr_dis, rx_fifo_not_empty, 4);
register_bit!(intr_dis, rx_fifo_full, 5);
register_bit!(intr_dis, tx_fifo_underflow, 6);
register!(enable, Enable, RW, u32);
register_bit!(enable, spi_en, 0);